Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions

On 9/6/22 13:22, Christoph Muellner wrote: +NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_sync_s, REQUIRE_PRIV_MHSU) These should not be nops

Re: [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension

On 9/6/22 13:22, Christoph Muellner wrote: @@ -732,6 +733,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadbs.c.inc" #include "decode-xtheadcmo.c.inc" #include "decode-xtheadcondmov.c.inc" +#include "decode-xtheadfmemidx.c.inc" #include "decode-xtheadmac.c.

Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs

On 9/6/22 13:22, Christoph Muellner wrote: +DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), +DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C910, rv64_thead_c906_cpu_init), Why model both if they're identical? r~

Re: [PATCH 3/3] target/ppc: Merge fsqrt and fsqrts helpers

On 9/6/22 15:22, Víctor Colombo wrote: On 05/09/2022 14:20, Richard Henderson wrote: Well, there would of course be no separate call, but I didn't understand what you meant here with 'no separate call'... We generate a separate call from tcg to helper_reset_fpstatus sometimes. Right, makes

Re: [PATCH v9 06/10] s390x/cpu_topology: resetting the Topology-Change-Report

On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote: > During a subsystem reset the Topology-Change-Report is cleared > by the machine. > Let's ask KVM to clear the Modified Topology Change Report (MTCR) > bit of the SCA in the case of a subsystem reset. > > Signed-off-by: Pierre Morel > --- >

[PATCH 1/2] Update linux headers to v6.0-rc4

commit 7e18e42e4b280c85b76967a9106a13ca61c16179 Signed-off-by: Chenyi Qiang --- include/standard-headers/asm-x86/bootparam.h | 7 +- include/standard-headers/drm/drm_fourcc.h | 73 +++- include/standard-headers/linux/ethtool.h | 29 +-- include/standard-headers/linux/input.h

[PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

After updating linux headers to v6.0-rc, clang build on x86 target would generate warnings like: target/i386/kvm/kvm.c:470:25: error: field 'info' with variable sized type 'struct kvm_msrs' not at the end of a struct or class is a GNU extension [-Werror,-Wgnu-variable-sized-type-not-at-end]

[PATCH 0/2] Update linux headers to v6.0-rc4 and fix the clang build error

After updating linux headers to v6.0-rc, clang build on x86 target would generate warnings related to -Wgnu-variable-sized-type-not-at-end. Simply turn off this warning in this patch set. If not suitable to turn it off, any comments or suggestions are welcome. Chenyi Qiang (2): Update linux hea

Re: [PATCH v2] audio: add help option for -audio and -audiodev

On 9/8/22 07:55, Volker Rümelin wrote: > Am 07.09.22 um 19:30 schrieb Claudio Fontana: > >> add a simple help option for -audio and -audiodev >> to show the list of available drivers, and document them. >> >> Signed-off-by: Claudio Fontana >> --- >> audio/audio.c | 20 >>

Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one

On 9/6/22 12:55, Claudio Fontana wrote: improve error handling during module load, by changing: bool module_load_one(const char *prefix, const char *lib_name); void module_load_qom_one(const char *type); to: bool module_load_one(const char *prefix, const char *name, Error **errp); bool module_

Re: [PULL 00/44] riscv-to-apply queue

On Wed, Sep 7, 2022 at 4:18 PM Stefan Hajnoczi wrote: > > On Wed, 7 Sept 2022 at 04:32, Alistair Francis via > wrote: > > > > The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: > > > > Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu > > into s

[PATCH v3] audio: add help option for -audio and -audiodev

add a simple help option for -audio and -audiodev to show the list of available drivers, and document them. Signed-off-by: Claudio Fontana --- audio/audio.c | 19 +++ audio/audio.h | 1 + qemu-options.hx | 10 ++ softmmu/vl.c| 9 +++-- 4 files changed, 33 in

Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs

On Thu, Sep 8, 2022 at 9:46 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 9/6/22 13:22, Christoph Muellner wrote: > > +DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, > rv64_thead_c906_cpu_init), > > +DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C910, > rv64_thead_c906_cpu_init), > > Why mod

Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one

Hi Richard, thanks for looking at this, On 9/8/22 10:11, Richard Henderson wrote: > On 9/6/22 12:55, Claudio Fontana wrote: >> improve error handling during module load, by changing: >> >> bool module_load_one(const char *prefix, const char *lib_name); >> void module_load_qom_one(const char *type)

Re: [PATCH v5 00/13] Instantiate VT82xx functions in host device

Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow : >v5: > >* Add patch "Inline vt82c686b_southbridge_init() and remove it" (Zoltan) > >* Use machine parameter when creating rtc-time alias (Zoltan) > > > >Testing done: Same as in v3. > > > >v4: > >* Fix in comment: AC97 Modem -> MC97 Modem

Re: [PATCH 00/42] Consolidate PIIX south bridges

Am 1. September 2022 16:25:31 UTC schrieb Bernhard Beschow : >This series consolidates the implementations of the PIIX3 and PIIX4 south > >bridges and is an extended version of [1]. The motivation is to share as much > >code as possible and to bring both device models to feature parity such that >

Re: [PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

On Thu, 8 Sept 2022 at 09:08, Chenyi Qiang wrote: > > After updating linux headers to v6.0-rc, clang build on x86 target would > generate warnings like: > > target/i386/kvm/kvm.c:470:25: error: field 'info' with variable sized > type 'struct kvm_msrs' not at the end of a struct or class is a GNU >

Re: [PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

On 9/8/22 09:07, Chenyi Qiang wrote: After updating linux headers to v6.0-rc, clang build on x86 target would generate warnings like: target/i386/kvm/kvm.c:470:25: error: field 'info' with variable sized type 'struct kvm_msrs' not at the end of a struct or class is a GNU extension [-Werror,-Wgnu

Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs

On 9/8/22 09:23, Christoph Müllner wrote: On Thu, Sep 8, 2022 at 9:46 AM Richard Henderson > wrote: On 9/6/22 13:22, Christoph Muellner wrote: > +    DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906,        rv64_thead_c906_cpu_init), > +    DEFINE_CPU(TY

Re: [PATCH v5 0/2] block: add missed block_acct_setup with new block device init procedure

Am 07.09.2022 um 19:25 hat Denis V. Lunev geschrieben: > ping I'll get to it (and quite a few other small series on the list that should be quick to review), but probably only after KVM Forum. So I'll have to ask you to be patient for a little longer. Kevin

Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs

On Thu, Sep 8, 2022 at 10:56 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 9/8/22 09:23, Christoph Müllner wrote: > > > > > > On Thu, Sep 8, 2022 at 9:46 AM Richard Henderson < > richard.hender...@linaro.org > > > wrote: > > > > On 9/6/22

Re: [PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

On Thu, Sep 08 2022, Peter Maydell wrote: > On Thu, 8 Sept 2022 at 09:08, Chenyi Qiang wrote: >> >> After updating linux headers to v6.0-rc, clang build on x86 target would >> generate warnings like: >> >> target/i386/kvm/kvm.c:470:25: error: field 'info' with variable sized >> type 'struct kvm_

Re: [PATCH v4 0/4] hw/ssi: ibex_spi: cleanup and fixup bugs

On Tue, Aug 23, 2022 at 8:12 AM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > Patch V4 fixes up: > - Fixup missing register field clearing on tx/rx_fifo_reset() in [2/4] > > Testing: > - Tested with Opentitan unit tests for TockOS...[OK] > > Wilfred Mallawa (4): > hw/ssi: ibex_sp

Re: [PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

On Thu, Sep 08, 2022 at 09:53:44AM +0100, Peter Maydell wrote: > On Thu, 8 Sept 2022 at 09:08, Chenyi Qiang wrote: > > > > After updating linux headers to v6.0-rc, clang build on x86 target would > > generate warnings like: > > > > target/i386/kvm/kvm.c:470:25: error: field 'info' with variable si

Re: [PATCH V4 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location

On Tue, Sep 6, 2022 at 11:38 AM Sunil V L wrote: > > load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same > function will be required by riscv too. So, it's time to refactor and > move this function to a common path. > > Signed-off-by: Sunil V L > Reviewed-by: Andrew Jones R

Re: [RFC PATCH] docs/system: clean up code escape for riscv virt platform

On Tue, Sep 6, 2022 at 2:26 PM Alex Bennée wrote: > > > Alistair Francis writes: > > > On Mon, Sep 5, 2022 at 6:39 PM Alex Bennée wrote: > >> > >> The example code is rendered slightly mangled due to missing code > >> block. Properly escape the code block and add shell prompt and qemu to > >> fi

Re: [PATCH V4 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel

On Tue, Sep 6, 2022 at 11:44 AM Sunil V L wrote: > > To enable both -kernel and -pflash options, the fw_cfg needs to be > created prior to loading the kernel. > > Signed-off-by: Sunil V L > Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 14 +++

Re: [PATCH] target/riscv: Remove sideleg and sedeleg

On Wed, Aug 24, 2022 at 4:54 PM Rahul Pathak wrote: > > sideleg and sedeleg csrs are not part of riscv isa spec > anymore, these csrs were part of N extension which > is removed from the riscv isa specification. > > These commits removed all traces of these csrs from > riscv spec (https://github.c

Re: [PATCH 2/2] target/riscv: fence: reconcile with specification

On Fri, Aug 12, 2022 at 4:19 PM Philipp Tomsich wrote: > > Happy to lower it back into the decode file. > However, I initially pulled it up into the trans-function to more > closely match the ISA specification: there is only one FENCE > instruction with 3 arguments (FM, PRED, and SUCC). > One migh

Re: [PATCH v3] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

On Wed, Aug 17, 2022 at 10:39 AM Weiwei Li wrote: > > - modify check for mcounteren to work in all less-privilege mode > - modify check for scounteren to work only when S mode is enabled > - distinguish the exception type raised by check for scounteren between U > and VU mode > > Signed-off-by: We

Re: [PATCH 2/2] target/riscv: fence: reconcile with specification

On Thu, 8 Sept 2022 at 11:25, Alistair Francis wrote: > > On Fri, Aug 12, 2022 at 4:19 PM Philipp Tomsich > wrote: > > > > Happy to lower it back into the decode file. > > However, I initially pulled it up into the trans-function to more > > closely match the ISA specification: there is only one

Re: [PATCH v3] audio: add help option for -audio and -audiodev

Queued, thanks. Paolo

[PATCH RESEND] hw/microblaze: pass random seed to fdt

If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This FDT node is part of the DT specification. Reviewed-by: Edgar E. Iglesias Signed-off-by: Jason A. Donenfeld --- hw/microblaze/boot.c |

[PATCH v1 6/9] hw/loongarch: Add RAMFB to dynamic_sysbus_devices list

Add RAMFB device to dynamic_sysbus_devices list so that it can be hotpluged to the machine. Signed-off-by: Xiaojuan Yang --- hw/loongarch/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index a3dd35d579..1e1dc699ef 100644 --- a/hw/loongarch/

[PATCH v1 0/9] Fix bugs and improve functions for LoongArch

These patches integrate all previous patches, including '[PATCH v1 0/2] Add mem hotplug and improve acpi dsdt (26 Aug )', '[PATCH v1] hw/loongarch: Fix acpi ged irq number in dsdt table (19 Aug)', '[PATCH v1 0/6] Add funtions for LoongArch virt machine (11 Aug)'. As none of the patches has not be

Re: [PATCH 3/4] msmouse: Add pnp data

Hi On Wed, Sep 7, 2022 at 2:05 AM Arwed Meyer wrote: > Make msmouse send serial pnp data. > Enables you to see nice qemu device name in Win9x. > > Signed-off-by: Arwed Meyer > --- > chardev/msmouse.c | 101 +++--- > 1 file changed, 68 insertions(+), 33 d

Re: [PATCH 2/4] chardev: src buffer const for write functions

Hi On Wed, Sep 7, 2022 at 2:05 AM Arwed Meyer wrote: > Make source buffers const for char be write functions. > This allows using buffers returned by fifo as buf parameter and source > buffer > should not be changed by write functions anyway. > > Signed-off-by: Arwed Meyer > Reviewed-by: Marc

[PATCH v1 8/9] hw/loongarch: Support memory hotplug

Add hotplug/unplug interface for memory device. Signed-off-by: Xiaojuan Yang --- hw/loongarch/Kconfig | 2 + hw/loongarch/acpi-build.c | 32 +--- hw/loongarch/virt.c | 105 +- 3 files changed, 132 insertions(+), 7 deletions(-) diff --git

Re: [PATCH 1/4] msmouse: Handle mouse reset

Hi On Wed, Sep 7, 2022 at 2:03 AM Arwed Meyer wrote: > Detect mouse reset via RTS or DTR line: > Don't send or process anything while in reset. > When coming out of reset, send ID sequence first thing. > This allows msmouse to be detected by common mouse drivers. > > Resolves: https://gitlab.com

[PATCH v1 9/9] hw/loongarch: Improve acpi dsdt table

Cleanup the previous pci information in acpi dsdt table. And using the common acpi_dsdt_add_gpex function to build the gpex and pci information. Signed-off-by: Xiaojuan Yang --- hw/loongarch/acpi-build.c | 159 +--- hw/loongarch/virt.c | 1 + include/h

[PATCH v1 4/9] hw/loongarch: Add platform bus support

Add platform bus support and add the bus information such as address, size, irq number to FDT table. Signed-off-by: Xiaojuan Yang --- hw/loongarch/Kconfig| 1 + hw/loongarch/virt.c | 33 + include/hw/loongarch/virt.h | 1 + include/hw/pci-host/ls

[PATCH v1 2/9] hw/loongarch: Support fw_cfg dma function

Support fw_cfg dma function for LoongArch virt machine. Signed-off-by: Xiaojuan Yang --- hw/loongarch/Kconfig | 1 + hw/loongarch/fw_cfg.c | 3 ++- hw/loongarch/virt.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 73c5

[PATCH v1 5/9] hw/loongarch: Add hotplug handler for machine

Add hotplug handler for LoongArch virt machine and now only support the dynamic sysbus device. Signed-off-by: Xiaojuan Yang --- hw/loongarch/virt.c | 32 1 file changed, 32 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 3976e8a058..a3

[PATCH v1 3/9] hw/loongarch: Add interrupt information to FDT table

Add interrupt information to FDT table, such as interrupt controller info, compatiable info, etc. Signed-off-by: Xiaojuan Yang --- hw/loongarch/virt.c | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 4f833a2044..56

[PATCH v1 1/9] hw/loongarch: Remove vga device when loongarch init

Remove the vga device when loongarch machine init and we will support other display device in the future. Signed-off-by: Xiaojuan Yang --- hw/loongarch/Kconfig | 1 - hw/loongarch/virt.c | 3 --- 2 files changed, 4 deletions(-) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index a99

[PATCH v1 7/9] hw/loongarch: Fix acpi ged irq number in dsdt table

In dsdt, acpi ged irq should use gsi number, and the VIRT_SCI_IRQ means it. Signed-off-by: Xiaojuan Yang --- hw/loongarch/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index d0f01a6485..95e30975a8 100644 ---

Re: [PATCH 4/4] serial: Allow unaligned i/o access

Hi On Wed, Sep 7, 2022 at 2:03 AM Arwed Meyer wrote: > Unaligned i/o access on serial UART works on real PCs. > This is used for example by FreeDOS CTMouse driver. Without this it > can't reset and detect serial mice. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/77 > Signed-off-by

Re: [PATCH v5 06/13] hw/isa/vt82c686: Instantiate IDE function in host device

On 9/1/22 08:41, Bernhard Beschow wrote: The IDE function is closely tied to the ISA function (e.g. the IDE interrupt routing happens there), so it makes sense that the IDE function is instantiated within the south bridge itself. Signed-off-by: Bernhard Beschow --- Acked-by: Daniel Henriqu

Re: [PATCH v5 05/13] hw/isa/vt82c686: Introduce TYPE_VIA_IDE define

On 9/1/22 08:41, Bernhard Beschow wrote: Establishes consistency with other (VIA) devices. Signed-off-by: Bernhard Beschow --- Acked-by: Daniel Henrique Barboza hw/ide/via.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/ppc/pegasos2.c | 2 +- include/hw/isa/vt82

Re: [PATCH v5 08/13] hw/isa/vt82c686: Instantiate USB functions in host device

On 9/1/22 08:41, Bernhard Beschow wrote: The USB functions can be enabled/disabled through the ISA function. Also its interrupt routing can be influenced there. Signed-off-by: Bernhard Beschow --- Acked-by: Daniel Henrique Barboza hw/isa/vt82c686.c | 12 hw/mips/fuloon

Re: [PATCH v5 07/13] hw/isa/vt82c686: Introduce TYPE_VT82C686B_USB_UHCI define

On 9/1/22 08:41, Bernhard Beschow wrote: Suggested-by: BALATON Zoltan Signed-off-by: Bernhard Beschow --- Acked-by: Daniel Henrique Barboza hw/mips/fuloong2e.c| 4 ++-- hw/ppc/pegasos2.c | 4 ++-- hw/usb/vt82c686-uhci-pci.c | 4 ++-- include/hw/isa/vt82c686.h | 1

Re: [PATCH v5 09/13] hw/isa/vt82c686: Instantiate PM function in host device

On 9/1/22 08:41, Bernhard Beschow wrote: The PM controller has activity bits which monitor activity of other built-in devices in the host device. Signed-off-by: Bernhard Beschow --- Acked-by: Daniel Henrique Barboza hw/isa/vt82c686.c | 13 + hw/mips/fuloong2e.c

Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflashy

On Wed, Sep 07, 2022 at 09:10:37AM +0200, Gerd Hoffmann wrote: > On Tue, Sep 06, 2022 at 06:02:00PM +0530, Sunil V L wrote: > > Hi Gerd, > > > > On Tue, Sep 06, 2022 at 12:41:28PM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > 3)Make the EDK2 image size to match with what qemu flash expect

Re: [PATCH v5 00/13] Instantiate VT82xx functions in host device

On 9/8/22 05:34, Bernhard Beschow wrote: Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow : v5: * Add patch "Inline vt82c686b_southbridge_init() and remove it" (Zoltan) * Use machine parameter when creating rtc-time alias (Zoltan) Testing done: Same as in v3. v4: * Fix in c

Re: [PATCH v5 13/13] hw/isa/vt82c686: Create rtc-time alias in boards instead

On 9/1/22 08:41, Bernhard Beschow wrote: According to good QOM practice, an object should only deal with objects of its own sub tree. Having devices create an alias on the machine object doesn't respect this good practice. To resolve this, create the alias in the machine's code. Signed-off-by

Re: [PATCH v5 10/13] hw/isa/vt82c686: Instantiate AC97 and MC97 functions in host device

On 9/1/22 08:41, Bernhard Beschow wrote: The AC97 function's wakeup status is wired to the PM function and both the AC97 and MC97 interrupt routing is determined by the ISA function. Signed-off-by: Bernhard Beschow --- Acked-by: Daniel Henrique Barboza hw/isa/vt82c686.c | 16 +++

Re: [PATCH v5 00/13] Instantiate VT82xx functions in host device

On Thu, 8 Sep 2022, Bernhard Beschow wrote: Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow : v5: * Add patch "Inline vt82c686b_southbridge_init() and remove it" (Zoltan) * Use machine parameter when creating rtc-time alias (Zoltan) Testing done: Same as in v3. v4: * Fix in c

[PATCH] migration: support file: uri for source migration

This is a prototype of supporting a 'file:' based uri protocol for writing out the migration stream of qemu. Currently the code always opens the file in DIO mode and adheres to an alignment of 64k to be generic enough. However this comes with a problem - it requires copying all data that we are wri

Re: [PATCH] chardev: fix segfault in finalize

On 8/25/22 19:52, Maksim Davydov wrote: If finalize chardev-msmouse or chardev-wctable is called immediately after init it cases QEMU to crash with segfault. This happens because of QTAILQ_REMOVE in qemu_input_handler_unregister tries to dereference NULL pointer. For instance, this error can be r

[PATCH 2/4] qmp: add dump machine type compatible properties

To control that creating new machine type doesn't affect the previous types (their compat_props) and to check complex compat_props inheritance we need qmp command to print machine type compatible properties. This patch adds the ability to get list of all the compat_props of the corresponding suppor

Re: [PATCH v6 14/14] qmp/hmp, device_tree.c: introduce dumpdtb

* Daniel Henrique Barboza (danielhb...@gmail.com) wrote: > To save the FDT blob we have the '-machine dumpdtb=' property. > With this property set, the machine saves the FDT in and exit. > The created file can then be converted to plain text dts format using > 'dtc'. > > There's nothing particula

[PATCH 1/4] qom: add devault value

qmp_qom_list_properties can print default values if they are available as qmp_device_list_properties does, because both of them use the ObjectPropertyInfo structure with default_value field. This can be useful when working with "not device" types. Signed-off-by: Maksim Davydov --- qom/qom-qmp-cm

[PATCH 0/4] compare machine type compat_props

This script is necessary to choose the best machine type in the appropriate cases. Also we have to check compat_props of the old MT after changes to be sure that they haven't broken old the MT. For example, pc_compat_3_1 of pc-q35-3.1 has Icelake-Client which was removed in March. changes: * new

[PATCH 3/4] python/qmp: increase read buffer size

After modification of "query-machines" command the buffer size should be more than 452kB to contain output with compat-props. Signed-off-by: Maksim Davydov --- python/qemu/qmp/qmp_client.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/python/qemu/qmp/qmp_client.py b/py

Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash

> Same thing can be adopted to arm also since both seem to follow the same > logic. But I think that will be a separate patch than this series. I > will run that as a separate RFC patch. Is that fine? Just to be clear, I meant RISC-V fix as separate RFC patch. Not the ARM. Thanks Sunil

[PATCH 4/4] scripts: add script to compare compatible properties

This script run QEMU to obtain compat_props of machines and default values of different types and produce appropriate table. This table can be used to compare machine types to choose the most suitable machine. Also table in json or csv format should be used to check that new machine doesn't affect

Re: [PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

On Thu, 8 Sept 2022 at 10:09, Daniel P. Berrangé wrote: > > On Thu, Sep 08, 2022 at 09:53:44AM +0100, Peter Maydell wrote: > > On Thu, 8 Sept 2022 at 09:08, Chenyi Qiang wrote: > > > > > > After updating linux headers to v6.0-rc, clang build on x86 target would > > > generate warnings like: > > >

Re: [PULL 00/10] QAPI patches patches for 2022-09-07

Am 07.09.2022 um 17:03 hat Markus Armbruster geschrieben: > The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: > > Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu > into staging (2022-09-06 08:31:24 -0400) > > are available in the Git reposito

Re: [PATCH 4/4] serial: Allow unaligned i/o access

On Thu, Sep 08, 2022 at 02:11:28PM +0400, Marc-André Lureau wrote: > Hi > > On Wed, Sep 7, 2022 at 2:03 AM Arwed Meyer wrote: > > Unaligned i/o access on serial UART works on real PCs. > This is used for example by FreeDOS CTMouse driver. Without this it > can't reset and detect seri

Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflashy

Hi, > Thanks Gerd. One question: Is it possible to have separate code + vars > even when there is TF-A? My understanding is, TF-A will take one drive > and will be hidden from the non-secure word. So, there is only one flash > left for edk2. Is that correct? Yes. > In RISC-V, I think we have t

[PATCH v3] 9pfs: use GHashTable for fid table

The previous implementation would iterate over the fid table for lookup operations, resulting in an operation with O(n) complexity on the number of open files and poor cache locality -- for every open, stat, read, write, etc operation. This change uses a hashtable for this instead, significantly i

Re: [PATCH v2 1/2] x86: only modify setup_data if the boot protocol indicates safety

On 09/06/22 13:33, Daniel P. Berrangé wrote: > On Tue, Sep 06, 2022 at 01:14:50PM +0200, Ard Biesheuvel wrote: >> (cc Laszlo) >> >> On Tue, 6 Sept 2022 at 12:45, Michael S. Tsirkin wrote: >>> >>> On Tue, Sep 06, 2022 at 12:43:55PM +0200, Jason A. Donenfeld wrote: On Tue, Sep 6, 2022 at 12:40

Re: [PATCH v4 2/4] hw/ssi: ibex_spi: fixup coverity issue

On Tue, Aug 23, 2022 at 8:13 AM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > This patch addresses the coverity issues specified in [1], > as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been > implemented to clean up the code. > > [1] https://www.mail-archive.com/qemu-devel@nongnu

[PATCH v2 1/2] [temporary] reserve bit KVM_HINTS_PHYS_ADDRESS_SIZE_DATA_VALID

The KVM_HINTS_PHYS_ADDRESS_SIZE_DATA_VALID bit hints to the guest that the size of the physical address space as advertised by CPUID leaf 0x8008 is actually valid and can be used. Unfortunately this is not the case today with qemu. Default behavior is to advertise 40 address bits (which I thi

[PATCH v2 2/2] [RfC] expose host-phys-bits to guest

Move "host-phys-bits" property from cpu->host_phys_bits to cpu->env.features[FEAT_KVM_HINTS] (KVM_HINTS_PHYS_ADDRESS_SIZE_DATA_VALID bit). This has the effect that the guest can see whenever host-phys-bits is turned on or not and act accordingly. Signed-off-by: Gerd Hoffmann --- target/i386/cpu

[PATCH v2 0/2] expose host-phys-bits to guest

When the guest (firmware specifically) knows how big the address space actually is it can be used better. Some more background: https://bugzilla.redhat.com/show_bug.cgi?id=2084533 This is a RfC series exposes the information via cpuid. v2: - change fvm hint name. - better commit message. ta

Re: [PATCH 2/2] configure: Add -Wno-gnu-variable-sized-type-not-at-end

On 9/8/22 10:09, Daniel P. Berrangé wrote: 'kvm_msrs info' is variable in size, so offset of 'entries[1]' is undefined by C99. I presume the GNU defined semantics are that the variable length 'entries[]' field in 'info' is zero-sized, in order to give predictable offset for 'entries[1]' in the lo

Re: [PULL 00/10] QAPI patches patches for 2022-09-07

Markus Armbruster writes: > Kevin Wolf writes: > >> Am 07.09.2022 um 17:03 hat Markus Armbruster geschrieben: >>> The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: >>> >>> Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu >>> into staging (20

Re: [PULL 00/10] QAPI patches patches for 2022-09-07

Kevin Wolf writes: > Am 07.09.2022 um 17:03 hat Markus Armbruster geschrieben: >> The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: >> >> Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu >> into staging (2022-09-06 08:31:24 -0400) >> >> are

Re: [PATCH] Use QMP command object-add instead of object_add for memory hotplugin

liuhaiwei writes: > From: liuhaiwei > > Signed-off-by: liuhaiwei > --- > docs/memory-hotplug.txt | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/docs/memory-hotplug.txt b/docs/memory-hotplug.txt > index 6aa5e17e26..85ed4d8f3d 100644 > --- a/docs/memory-hotplug.

Re: [PATCH 1/4] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan

On Fri, Sep 2, 2022 at 3:29 AM Tyler Ng wrote: > > This commit adds most of an implementation of the OpenTitan Always-On > Timer. The documentation for this timer is found here: > > https://docs.opentitan.org/hw/ip/aon_timer/doc/ > > The implementation includes most of the watchdog features; it do

Re: [PATCH 3/4] hw/timer: ibex_timer.c: Update register addresses

On Fri, Sep 2, 2022 at 3:24 AM Tyler Ng wrote: > > Updates the register addresses to match the OpenTitan spec. > > These changes were made in this commit: > https://github.com/lowRISC/opentitan/commit/a25e162b8f91bd0ca32258c83d1d480f93327204 Thanks for the patch We try to keep all OpenTitan devi

Re: [PATCH v4 2/9] target/arm: Change gen_goto_tb to work on displacements

On 9/6/22 13:52, Philippe Mathieu-Daudé wrote: @@ -1399,9 +1401,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)   tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,   tcg_cmp, 0, label_match); -    gen_goto_tb(s, 0, s->base.pc_next); +    gen_goto_t

Re: [PATCH v2 02/23] target/i386: Return bool from disas_insn

On 9/6/22 15:42, Philippe Mathieu-Daudé wrote: On 6/9/22 12:09, Richard Henderson wrote: Instead of returning the new pc, which is present in DisasContext, return true if an insn was translated. This is false when we detect a page crossing and must undo the insn under translation. Signed-off-by

Re: [PATCH v3] 9pfs: use GHashTable for fid table

On Thu, 8 Sep 2022 13:23:53 +0200 Linus Heckemann wrote: > The previous implementation would iterate over the fid table for > lookup operations, resulting in an operation with O(n) complexity on > the number of open files and poor cache locality -- for every open, > stat, read, write, etc operat

Re: [PATCH 4/4] hw/timer: ibex_timer.c: Add support for writes to mtime

On Fri, Sep 2, 2022 at 3:28 AM Tyler Ng wrote: > > 1. Adds fields to hold the value of mtime in timer_upper0 and timer_lower0. > > 2. Changes the read and write functions to use the mtime fields. > > 3. Updates the value of mtime in update_mtime() by extrapolating the > time elapsed. This will nee

Re: [PATCH 1/2] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml

On Wed, Aug 31, 2022 at 10:43 AM Andrew Burgess wrote: > > While testing some changes to GDB's handling for the RISC-V registers > fcsr, fflags, and frm, I spotted that QEMU includes these registers > twice in the target description it sends to GDB, once in the fpu > feature, and once in the csr f

Re: [PATCH] target/riscv: Remove sideleg and sedeleg

On Wed, Aug 24, 2022 at 4:54 PM Rahul Pathak wrote: > > sideleg and sedeleg csrs are not part of riscv isa spec > anymore, these csrs were part of N extension which > is removed from the riscv isa specification. > > These commits removed all traces of these csrs from > riscv spec (https://github.c

Re: [PATCH v2 1/2] x86: only modify setup_data if the boot protocol indicates safety

On Thu, 8 Sept 2022 at 13:30, Laszlo Ersek wrote: > > On 09/06/22 13:33, Daniel P. Berrangé wrote: > > On Tue, Sep 06, 2022 at 01:14:50PM +0200, Ard Biesheuvel wrote: > >> (cc Laszlo) > >> > >> On Tue, 6 Sept 2022 at 12:45, Michael S. Tsirkin wrote: > >>> > >>> On Tue, Sep 06, 2022 at 12:43:55PM

Re: [PATCH v3] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

On Wed, Aug 17, 2022 at 10:39 AM Weiwei Li wrote: > > - modify check for mcounteren to work in all less-privilege mode > - modify check for scounteren to work only when S mode is enabled > - distinguish the exception type raised by check for scounteren between U > and VU mode > > Signed-off-by: We

Re: [PATCH] Use QMP command object-add instead of object_add for memory hotplugin

liuhaiwei9699 writes: > why the hmp using the object_add , qmp using the object-add command? > can't we use the same command ? Command names differ between HMP and QMP for historical reasons. QMP is a stable interface, and changing names there is no go. HMP is not a stable interface, but chan

Re: [PATCH 2/2] target/riscv: remove fixed numbering from GDB xml feature files

On Wed, Aug 31, 2022 at 10:45 AM Andrew Burgess wrote: > > The fixed register numbering in the various GDB feature files for > RISC-V only exists because these files were originally copied from the > GDB source tree. > > However, the fixed numbering only exists in the GDB source tree so > that GDB

Re: [PATCH v2 1/2] x86: only modify setup_data if the boot protocol indicates safety

On Thu, Sep 08, 2022 at 02:28:29PM +0200, Ard Biesheuvel wrote: > On Thu, 8 Sept 2022 at 13:30, Laszlo Ersek wrote: > > > > On 09/06/22 13:33, Daniel P. Berrangé wrote: > > > On Tue, Sep 06, 2022 at 01:14:50PM +0200, Ard Biesheuvel wrote: > > >> (cc Laszlo) > > >> > > >> On Tue, 6 Sept 2022 at 12:

[PATCH] migrate block dirty bitmap: Fix the block dirty bitmap can't to migration_completion when pending size larger than threshold size : 1、dirty bitmap size big enough (such as 8MB) when block si

From: liuhaiwei so we set the fake pending size when pending size > threshold size Signed-off-by: liuhaiwei Signed-off-by: liuhaiwei --- migration/block-dirty-bitmap.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirt

Access DomU shared memory in Dom0 Kernel

Hi, I am mapping DomU DMA Address in Qemu source using dma_memory_map API. But my Dom0's kernel is unable to access the VA assigned to dma_memory_map API in Qemu. Any Suggestion? Sent with [Proton Mail](https://proton.me/) secure email.

[PATCH] Use QMP command object-add instead of object_add for memory hotplugin

From: liuhaiwei Signed-off-by: liuhaiwei --- docs/memory-hotplug.txt | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/memory-hotplug.txt b/docs/memory-hotplug.txt index 6aa5e17e26..85ed4d8f3d 100644 --- a/docs/memory-hotplug.txt +++ b/docs/memory-hotplug.txt @@ -

[PATCH] qemu-img: Wean documentation and help output off '?' for help

'?' for help is deprecated since commit c8057f951d "Support 'help' as a synonym for '?' in command line options", v1.2.0. We neglected to update output of qemu-img --help and the manual. Do that now. Signed-off-by: Markus Armbruster --- docs/tools/qemu-img.rst | 2 +- qemu-img.c |

Re:Re: [PATCH] Use QMP command object-add instead of object_add for memory hotplugin

why the hmp using the object_add , qmp using the object-add command? can't we use the same command ? At 2022-09-08 19:41:33, "Markus Armbruster" wrote: >liuhaiwei writes: > >> From: liuhaiwei >> >> Signed-off-by: liuhaiwei >> --- >> docs/memory-hotplug.txt | 8 >> 1 f

Re: [PATCH] Use QMP command object-add instead of object_add for memory hotplugin

* Markus Armbruster (arm...@redhat.com) wrote: > liuhaiwei9699 writes: > > > why the hmp using the object_add , qmp using the object-add command? > > can't we use the same command ? > > Command names differ between HMP and QMP for historical reasons. > > QMP is a stable interface, and changing

[PATCH 0/7] nsis: gitlab-ci: Improve QEMU Windows installer packaging

At present packaging the required DLLs of QEMU executables is a manual process, and error prone. Improve scripts/nsis.py by adding a logic to automatically package required DLLs of QEMU executables. 'make installer' is tested in the cross-build on Linux in CI, but not in the Windows native build.

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