On Wed, Aug 24, 2022 at 4:54 PM Rahul Pathak <rpat...@ventanamicro.com> wrote: > > sideleg and sedeleg csrs are not part of riscv isa spec > anymore, these csrs were part of N extension which > is removed from the riscv isa specification. > > These commits removed all traces of these csrs from > riscv spec (https://github.com/riscv/riscv-isa-manual) - > > commit f8d27f805b65 ("Remove or downgrade more references to N extension > (#674)") > commit b6cade07034d ("Remove N extension chapter for now") > > Signed-off-by: Rahul Pathak <rpat...@ventanamicro.com> > Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Thanks! Applied to riscv-to-apply.next Alistair > --- > disas/riscv.c | 2 -- > target/riscv/cpu_bits.h | 2 -- > 2 files changed, 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index 7af6afc8fa..a709d66167 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1304,8 +1304,6 @@ static const char *csr_name(int csrno) > case 0x0043: return "utval"; > case 0x0044: return "uip"; > case 0x0100: return "sstatus"; > - case 0x0102: return "sedeleg"; > - case 0x0103: return "sideleg"; > case 0x0104: return "sie"; > case 0x0105: return "stvec"; > case 0x0106: return "scounteren"; > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 6be5a9e9f0..7251121218 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -190,8 +190,6 @@ > > /* Supervisor Trap Setup */ > #define CSR_SSTATUS 0x100 > -#define CSR_SEDELEG 0x102 > -#define CSR_SIDELEG 0x103 > #define CSR_SIE 0x104 > #define CSR_STVEC 0x105 > #define CSR_SCOUNTEREN 0x106 > -- > 2.34.1 > >
