On Thu, 8 Sept 2022 at 11:25, Alistair Francis <alistai...@gmail.com> wrote: > > On Fri, Aug 12, 2022 at 4:19 PM Philipp Tomsich > <philipp.toms...@vrull.eu> wrote: > > > > Happy to lower it back into the decode file. > > However, I initially pulled it up into the trans-function to more > > closely match the ISA specification: there is only one FENCE > > instruction with 3 arguments (FM, PRED, and SUCC). > > One might argue that the decode table for "RV32I Base Instruction Set" > > in the specification lists FENCE.TSO as a separate instruction, but > > the normative text doesn't (and FENCE overlaps FENCE.TSO in the > > tabular representation) — so I would consider the table as > > informative. > > > > I'll wait until we see what consensus emerges from the discussion. > > From the discussion on patch 1 it seems that QEMU ignoring these > fields (current behaviour) is correct
Yes, this is an accurate reading of the situation. Philipp.
