On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> Introduce A25 and AX25 CPU model designed by Andes Technology.
>
> Signed-off-by: Ruinland Chuan-Tzu Tsai
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 16
> target/riscv/cpu.h | 2 ++
>
On Thu, Oct 21, 2021 at 4:04 PM Richard Henderson
wrote:
>
> On 9/10/21 4:26 AM, Luis Pires wrote:
> > Introduce uabs64(), a function that returns the absolute value of
> > a 64-bit int as an unsigned value. This avoids the undefined behavior
> > for common abs implementations, where abs of the mo
On Fri, Oct 22, 2021 at 2:30 AM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
It doesn't look like this made it through to the list. I only see v3
on patchew:
https://patchew.org/QEMU/20
On 9/10/21 4:26 AM, Luis Pires wrote:
-#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2)\
-static void gen_##name(DisasContext *ctx) \
-{ \
-TCGv_ptr rt, rb; \
-TCGv_i32 u32_1, u32_2;
On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> riscv_csrrw() will be called by CSR handling helpers, which is the
> most suitable place for checking wheter a custom CSR is being accessed.
>
> If we're touching a custom CSR, invoke the registered handlers.
>
> Signed-off-by: Rui
On 9/10/21 4:26 AM, Luis Pires wrote:
-#define GEN_DFP_T_B_Rc(name) \
-static void gen_##name(DisasContext *ctx)\
-{\
-TCGv_ptr rt, rb; \
-if (unlikely(!ctx->fpu_enabled)) { \
On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> Add CSR bits definitions, CSR table and handler functions for Andes
> AX25 and A25 CPUs. Also, enable the logic in a(x)25_cpu_init().
>
> Signed-off-by: Ruinland Chuan-Tzu Tsai
> ---
> target/riscv/andes_cpu_bits.h | 129 +++
On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> Hi Alistair, Bin and all :
>
> Sorry for bumping this stale topic.
> As our last discussion, I have removed Kconfigs and meson options.
> The custom CSR logic is in-built by default and whether a custom CSR
> is presented on the ac
On Wed, Oct 20, 2021 at 8:43 PM Alexey Baturo wrote:
>
> v14:
> Addressed Richard's comments from previous series.
>
> v13:
> Rebased QEMU and addressed Richard's comment.
>
> v12:
> Updated function for adjusting address with pointer masking to allocate and
> use temp register.
>
> v11:
> Addres
On 9/10/21 4:26 AM, Luis Pires wrote:
-#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
-static void gen_##name(DisasContext *ctx) \
-{ \
-TCGv_ptr rt, rs; \
-TCGv_i32 i32;
On 10/21/21 3:34 PM, Eduardo Habkost wrote:
On Thu, Oct 21, 2021 at 4:04 PM Richard Henderson
wrote:
On 9/10/21 4:26 AM, Luis Pires wrote:
Introduce uabs64(), a function that returns the absolute value of
a 64-bit int as an unsigned value. This avoids the undefined behavior
for common abs imp
On 10/21/21 3:31 PM, Alistair Francis wrote:
On Fri, Oct 22, 2021 at 2:30 AM wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
It doesn't look like this made it through to the list. I only see v3
on
On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote:
riscv_csrrw() will be called by CSR handling helpers, which is the
most suitable place for checking wheter a custom CSR is being accessed.
If we're touching a custom CSR, invoke the registered handlers.
Signed-off-by: Ruinland Chuan-Tzu Tsai
WANG Xuerui wrote:
> Song Gao wrote:
> > Account yangxiaoj...@loongson.cn It seems that she has been
> > blacklisted. Xiaojuan sent 31 e-mails, which were not displayed
> > since the 21st one, people who don't have a CC can't read all the
> > emails, and xiaojuan reply can't be in qemu-le...@nongn
On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote:
diff --git a/target/riscv/csr_andes.c b/target/riscv/csr_andes.c
new file mode 100644
index 00..8617f40483
--- /dev/null
+++ b/target/riscv/csr_andes.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2021 Andes Technology Corp.
+ * SPDX-License-
Hi,Bob
Thank you for your advice, I'll try.
Thanks
Xiaojuan, Yang
在 2021年10月22日 08:12, Bob Proulx 写道:
> WANG Xuerui wrote:
>> Song Gao wrote:
>>> Account yangxiaoj...@loongson.cn It seems that she has been
>>> blacklisted. Xiaojuan sent 31 e-mails, which were not displayed
>>> since the 21st
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
This patch series implements 56 new instructions for POWER10, moving 28
"old" instructions to decodetree along the way. The series is divided by
facility as follows:
- From patch 1 to 4: Floating-Point
- From patch 5
Hi, Alex,
On Thu, Oct 21, 2021 at 04:30:39PM -0600, Alex Williamson wrote:
> On Thu, 21 Oct 2021 18:42:59 +0800
> Peter Xu wrote:
>
> > Scan the pci bus to make sure there's no vfio-pci device attached before
> > vIOMMU
> > is realized.
>
> Sorry, I'm not onboard with this solution at all.
>
On Thu, Oct 21, 2021 at 01:15:03PM +0200, Eric Auger wrote:
> Hi Peter,
>
> On 10/21/21 12:42 PM, Peter Xu wrote:
> > It's used in quite a few places of pci.c and also in the rest of the code
> > base.
> > Define such a hook so that it doesn't need to be defined all over the
> > places.
> >
> >
On Thu, Oct 21, 2021 at 01:34:07PM +0200, Eric Auger wrote:
> Hi Peter,
> On 10/21/21 12:42 PM, Peter Xu wrote:
> > Replace all the call sites of existing pci_for_each_device*() where the bus
> > number is calculated from a PCIBus* already. It should avoid the lookup of
> > the
> > PCIBus again.
On Thu, Oct 21, 2021 at 02:54:44PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/21/21 13:44, Philippe Mathieu-Daudé wrote:
> > On 10/21/21 12:42, Peter Xu wrote:
> >> The pci_bus_fn is similar to pci_bus_dev_fn that only takes a PCIBus* and
> >> an
> >> opaque. The pci_bus_ret_fn is similar to pc
在 2021年10月20日 02:56, Richard Henderson 写道:
> On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
>> ---
>> target/loongarch/README | 134 +++
>> target/loongarch/ramdisk | Bin 0 -> 3077952 bytes
>> target/loongarch/vmlinux | Bin 0 -> 24565536 bytes
>> 3 files c
Hi, Michael,
On Thu, Oct 21, 2021 at 06:54:59AM -0400, Michael S. Tsirkin wrote:
> > +typedef struct {
> > +pci_bus_dev_fn fn;
> > +void *opaque;
> > +} pci_bus_dev_args;
>
> code style violation. CamelCase for structs pls.
OK.
> > +/* Call 'fn' for each pci device on the system */
> >
On Thu, Oct 21, 2021 at 02:38:54PM +0200, Eric Auger wrote:
> Hi Peter,
>
> On 10/21/21 12:42 PM, Peter Xu wrote:
> > Scan the pci bus to make sure there's no vfio-pci device attached before
> > vIOMMU
> > is realized.
> >
> > Suggested-by: Igor Mammedov
> > Signed-off-by: Peter Xu
> > ---
> >
On Fri, Oct 22, 2021 at 7:28 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 10/21/21 3:31 PM, Alistair Francis wrote:
> > On Fri, Oct 22, 2021 at 2:30 AM wrote:
> >>
> >> From: Kito Cheng
> >>
> >> Signed-off-by: Kito Cheng
> >> Signed-off-by: Chih-Min Chao
> >> Signed-off-by
From: Alistair Francis
Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/virt.h | 1 -
hw/riscv/virt.c
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fc5790b8ce..0010b404ee 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@
From: Alistair Francis
Add a generic function that can create the PLIC strings.
Signed-off-by: Alistair Francis
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 25 +
2 files changed, 27 insertions(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/risc
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2d3a8ec405..8715cfe659 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -748,24 +748,6
From: Alistair Francis
Signed-off-by: Alistair Francis
---
include/hw/riscv/microchip_pfsoc.h | 1 -
hw/riscv/microchip_pfsoc.c | 14 +-
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
i
Le 20/10/2021 à 16:44, Richard Henderson a écrit :
> On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
>> The upper 64-bit of the 128-bit registers have now a place inside
>> the cpu state structure, and are created as globals for future use.
>>
>> Signed-off-by: Frédéric Pétrot
>> Co-authored-by: Fabie
And the FMC registers are just an alias to write
to these watchdog 2 registers?
If this is the same watchdog mapped into the FMC, I would say yes
and the logic generate load/stores transactions on the AHB bus.
Adding an address space for the WDT registers in the model is the
closer we can get w
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