Le 20/10/2021 à 16:44, Richard Henderson a écrit :
> On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
>> The upper 64-bit of the 128-bit registers have now a place inside
>> the cpu state structure, and are created as globals for future use.
>>
>> Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
>> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
>> ---
>> target/riscv/translate.c | 5 ++++-
>> 2 files changed, 5 insertions(+), 1 deletion(-)
>> for (i = 1; i < 32; i++) {
>> cpu_gpr[i] = tcg_global_mem_new(cpu_env,
>> offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
>> + cpu_gprh[i] = tcg_global_mem_new(cpu_env,
>> + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
>
> This will just be confusing in the tcg dumps -- let's not name the two temps
> the
> identically.
Agreed.
> Honestly, I'm not 100% thrilled about the / that appears in the current name;
> I
> think it would be easiest to do
>
> g_string_printf("x%d", i)
> and
> g_string_printf("x%dh", i)
Registers sw names are used by gcc -S and the default objdump -d output,
and also by disas/riscv.c, so dropping them might be a bit rough.
For now I'll just add an h in the existing names, and suggest we wait to see
if anyone cares.
Frédéric
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
