On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai <ruinl...@andestech.com> wrote: > > Hi Alistair, Bin and all : > > Sorry for bumping this stale topic. > As our last discussion, I have removed Kconfigs and meson options. > The custom CSR logic is in-built by default and whether a custom CSR > is presented on the accessing hart will be checked at runtime.
No worries! This looks great! I had a look through this and I think we are almost there. I left a few comments, but otherwise I think we are close. Let's see if anyone else has any comments. Otherwise can you run checkpatch on each patch and then send a PATCH series (not an RFC) in a week or so and we can go from there. > > Changes from V4 : > Remove Kconfigs and meson options. > Make custom CSR handling logic self-contained. > Use g_hash_table_new instead of g_hash_table_new_full. > > The performance slowdown could be easily tested with a simple program > running on linux-user mode : > > /* test_csr.c */ > #include <stdio.h> > #include <unistd.h> > #include <sys/time.h> > > int main (int ac, char *av[]) { > struct timeval start; > struct timeval end; > gettimeofday(&start,NULL); > unsigned int loop_n = 999999 ; > unsigned char i; > unsigned char o; > do { > for(i=0; i<32; i++) { > #if defined(FCSR) > __asm__("csrw fcsr, %0;"::"r"(i)); > __asm__("csrr %0, fcsr;":"=r"(o)); > #elif defined(UITB) > __asm__("csrw 0x800, %0;"::"r"(i)); > __asm__("csrr %0, 0x800;":"=r"(o)); > #endif > } > --loop_n; > } while (loop_n > 0); > gettimeofday(&end,NULL); > unsigned long diff = 1000000 * > (end.tv_sec-start.tv_sec)+end.tv_usec-start.tv_usec; > printf("%f\n", (double)(diff)/1000000); > return 0; > } > > $ riscv64-linux-gnu-gcc -static -DUITB ./test_csr.c -o ./u > $ riscv64-linux-gnu-gcc -static -DFCSR ./test_csr.c -o ./f > $ qemu-riscv64 ./{u,f} Do you have the results? Alistair > > Cordially yours, > Ruinland Chuan-Tzu Tsai > > Ruinland Chuan-Tzu Tsai (3): > riscv: Adding Andes A25 and AX25 cpu models > riscv: Introduce custom CSR hooks to riscv_csrrw() > riscv: Enable custom CSR support for Andes AX25 and A25 CPUs > > target/riscv/andes_cpu_bits.h | 129 +++++++++++++++++++++++ > target/riscv/cpu.c | 39 +++++++ > target/riscv/cpu.h | 15 ++- > target/riscv/csr.c | 38 +++++-- > target/riscv/csr_andes.c | 183 +++++++++++++++++++++++++++++++++ > target/riscv/custom_csr_defs.h | 8 ++ > target/riscv/meson.build | 1 + > 7 files changed, 404 insertions(+), 9 deletions(-) > create mode 100644 target/riscv/andes_cpu_bits.h > create mode 100644 target/riscv/csr_andes.c > create mode 100644 target/riscv/custom_csr_defs.h > > -- > 2.25.1 >