On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote:
diff --git a/target/riscv/csr_andes.c b/target/riscv/csr_andes.c
new file mode 100644
index 0000000000..8617f40483
--- /dev/null
+++ b/target/riscv/csr_andes.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2021 Andes Technology Corp.
+ * SPDX-License-Identifier: GPL-2.0+
+ * Andes custom CSR table and handling functions
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "cpu.h"
+#include "qemu/main-loop.h"
+#include "exec/exec-all.h"
+#include "andes_cpu_bits.h"
+
+struct andes_csr_val {
+ target_long uitb;
+};
docs/devel/style.rst: Use a typedef and CamelCase.
And of course per review of patch 2, this needs to go elsewhere.
You need to add a subsection to machine.c to migrate this new state. With respect to the
custom instructions, I suggested adding an ext_andes field. I would expect these CSRs,
which go with those instructions, to use the same predicate.
+riscv_custom_csr_operations andes_custom_csr_table[MAX_CUSTOM_CSR_NUM] = {
...
+ {CSR_TXEVT, { "csr_txevt", any, read_zero, write_stub}
},
+ {0, { "", NULL, NULL, NULL } },
+ };
Indentation here.
I think you should not export the array itself, but instead
void andes_setup_custom_csrs(RISCVCPUClass *cc)
{
setup_custom_csrs(cc, andes_custom_csr_table,
ARRAY_SIZE(andes_custom_csr_table));
}
r~
