When ACPI hotplug for the root bus is disabled, the bsel property for that
bus is not set. Please see the following commit:
3d7e78aaf ("Introduce a new flag for i440fx to disable PCI hotplug on the
root bus").
As a result, when acpi_pcihp_find_hotplug_bus() is called
with bsel set to 0, it m
#define QEMU_PKGVERSION ""
#define QEMU_FULL_VERSION "5.1.50"
pkgversion=$(git describe --match 'v*' --dirty | echo "")
what's echo "" for in qemu-version.sh
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
Configure used to probe for SDL2_image in sdl_image_probe (). Meson
should do the same.
This fixes the following error on my system:
Run-time dependency sdl2 found: YES 2.0.8
Found CMake: /usr/bin/cmake (3.17.0)
Run-time dependency sdl-image found: NO (tried pkgconfig and cmake)
../qemu-master/m
Linux userspace always sees coprocessors as enabled. CPENABLE register
and coprocessor exceptions are used internally by the kernel to manage
lazy coprocessor context switch. None of it is needed for linux-user.
Always enable all coprocessors for user emulation.
Signed-off-by: Max Filippov
---
t
On Fri, Aug 28, 2020 at 5:18 PM 罗勇刚(Yonggang Luo) wrote:
>
> I am confusing, why my patch are not recognized by Patchew?
I looked at the message headers in case git-publish corrupted the
email, but I didn't notice any issues.
Some of your other patches were detected correctly by Patchew:
https:/
** Tags added: linux-user
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1893040
Title:
External modules retreval using Go1.15 on s390x appears to have
checksum and ECDSA verification issues
Sta
On Sat, 29 Aug 2020 at 00:24, Richard Henderson
wrote:
>
> On 8/28/20 11:33 AM, Peter Maydell wrote:
> > +#define float16_nop(N, M, S) (M)
> > +#define float32_nop(N, M, S) (M)
> > +#define float64_nop(N, M, S) (M)
> >
> > +DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16, H2)
> > +DO_FMUL_IDX(gvec_fmul_
On Sat, 29 Aug 2020 at 00:38, Richard Henderson
wrote:
>
> On 8/28/20 11:33 AM, Peter Maydell wrote:
> > Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec,
> > and use this to implement fp16 support.
> >
> > Signed-off-by: Peter Maydell
>
> Reviewed-by: Richard Henderson
>
> > +
On Fri, 28 Aug 2020 at 23:53, Richard Henderson
wrote:
>
> On 8/28/20 2:40 PM, Peter Maydell wrote:
> > The other approach would be to standardize on "the decodetree pattern
> > always converts the size to the data-type size, regardless of how
> > it's encoded in the insn fields", and then you cou
Please check qemu-5.1.0.
This has been fixed by:
2d92c6827ca0 ("linux-user: implement OFD locks")
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=2d92c6827ca0
perhaps you can send a patch to the qemu-devel ML to add the strace
part.
--
You received this bug notification because you are a m
On 2020/8/29 1:53, Richard Henderson wrote:
These operations were missed in Zhiwei's bfloat16 implementation.
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 41 +
1 file changed, 41 insertions(+)
diff --git a/include/fpu/softfloat.h
From: Bin Meng
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Men
From: Bin Meng
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no ch
From: Bin Meng
This adds support for Microchip PolarFire SoC Icicle Kit board.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire SoC, please see:
https://www.microsemi.co
From: Bin Meng
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.
Signed-off-by: Bin Meng
---
Changes in v2:
- connect 8 IRQs to the PLIC
include/hw/r
From: Bin Meng
This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire Soc, please see:
https://www.microsemi
From: Bin Meng
Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.
This creates a model to support b
From: Bin Meng
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a config
From: Bin Meng
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng
---
(no changes since v1)
include/hw/riscv/sifive_u.h | 11 +++
hw/riscv/s
From: Bin Meng
Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.
Signed-off-by: Bin Meng
---
Changes in v2:
- change to update hw/char/meson.build
- add impl.min_access_size and impl.m
From: Bin Meng
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/riscv/microchip_pfsoc.h | 20
hw/riscv/microchip_p
From: Bin Meng
When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY add
From: Bin Meng
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(
From: Bin Meng
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. C
From: Bin Meng
At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.
Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.
Signed-off-by: Bin
From: Bin Meng
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.
As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test th
From: Bin Meng
At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.
Signed-off-by: Bin Meng
---
Chan
From: Bin Meng
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.
The 2nd stage bootloader (U-Boot) is using GEM1
Hi Haibo,
On 8/7/20 10:10 AM, Haibo Xu wrote:
> Add a virtual SPE device for virt machine while using PPI
> 5 for SPE overflow interrupt number.
>
> Signed-off-by: Haibo Xu
> ---
> hw/arm/virt-acpi-build.c| 3 +++
> hw/arm/virt.c | 42 +
>
On 8/29/20 6:53 AM, Peter Maydell wrote:
> On Fri, 28 Aug 2020 at 23:53, Richard Henderson
> wrote:
>>
>> On 8/28/20 2:40 PM, Peter Maydell wrote:
>>> The other approach would be to standardize on "the decodetree pattern
>>> always converts the size to the data-type size, regardless of how
>>> it'
On 8/27/20 12:17 PM, Edgar E. Iglesias wrote:
> On Tue, Aug 25, 2020 at 01:59:35PM -0700, Richard Henderson wrote:
>> If the last insn on a page is imm, or a branch with delay slot,
>> then end a tb early if this has not begun the tb. If it has
>> begun the tb, then we can allow the tb to span two
On Fri, Aug 28, 2020 at 9:38 PM Paolo Bonzini wrote:
>
> Meson includes the same logic that tries to look for -lz if
> pkg-config (and cmake) cannot find zlib. The undocumented
> --disable-zlib-test option becomes a no-op.
>
> Signed-off-by: Paolo Bonzini
Nice! (special treatment since 0.54),
R
On 8/29/20 3:47 AM, Max Filippov wrote:
> Linux userspace always sees coprocessors as enabled. CPENABLE register
> and coprocessor exceptions are used internally by the kernel to manage
> lazy coprocessor context switch. None of it is needed for linux-user.
> Always enable all coprocessors for user
On 8/22/20 7:21 AM, Philippe Mathieu-Daudé wrote:
> The S24/TCX datasheet is listed as "Unable to locate" on [1].
>
> However the NetBSD revision 1.32 of the driver introduced
> 64-bit accesses to the stippler and blitter [2]. It is safe
> to assume these memory regions are 64-bit accessible.
> QE
On 8/22/20 9:14 AM, Philippe Mathieu-Daudé wrote:
> There is an issue when accessing an alias memory region via the
> memory_region_dispatch_read() / memory_region_dispatch_write()
> calls.
>
> Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all
> regions") we assign &unassigned_mem_op
On 8/17/20 1:48 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> * Remove VXRM and VXSAT fields from FCSR register as they are only
> presented in VCSR register.
> * Remove RVV loose check in fs() predicate function.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/csr.c | 13 ---
On 2020/8/26 6:30, Alistair Francis wrote:
On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell wrote:
On Tue, 25 Aug 2020 at 22:32, Alistair Francis wrote:
On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell wrote:
The hypervisor related patches don't seem to have any
reviewed-by tags, which seems a
On 8/17/20 1:48 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Introduce the concepts of fractional LMUL for RVV 1.0.
> In RVV 1.0, LMUL bits are contiguous in vtype register.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/cpu.h | 15 ---
> target/riscv/tr
Le sam. 29 août 2020 18:14, Michael a écrit :
> Hello,
>
> since I wrote the NetBSD code in question, here are my 2 cent:
>
> On Sat, 29 Aug 2020 08:41:43 -0700
> Richard Henderson wrote:
>
> > On 8/22/20 7:21 AM, Philippe Mathieu-Daudé wrote:
> > > The S24/TCX datasheet is listed as "Unable to
Hello,
since I wrote the NetBSD code in question, here are my 2 cent:
On Sat, 29 Aug 2020 08:41:43 -0700
Richard Henderson wrote:
> On 8/22/20 7:21 AM, Philippe Mathieu-Daudé wrote:
> > The S24/TCX datasheet is listed as "Unable to locate" on [1].
I don't have it either, but someone did a lot
On Sat, Aug 29, 2020 at 8:50 AM LIU Zhiwei wrote:
>
>
>
> On 2020/8/26 6:30, Alistair Francis wrote:
> > On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell
> > wrote:
> >> On Tue, 25 Aug 2020 at 22:32, Alistair Francis
> >> wrote:
> >>> On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell
> >>> wrote:
>
On 8/17/20 1:48 AM, frank.ch...@sifive.com wrote:
> +static inline bool is_aligned(const uint8_t val, const uint8_t pos)
> +{
> +return pos ? (val & (pos - 1)) == 0 : true;
> +}
The truncation to uint8_t from int is odd. Can we drop all of that and just
use int?
Looking at the uses, I think
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Immediate value in translator function is extended not only
> zero-extended and sign-extended but with more modes to be applicable
> with multiple formats of vector instructions.
>
> * IMM_ZX: Zero-extended
> * IMM
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> * Add fp16 nan-box check generator function, if a 16-bit input is not
> properly nanboxed, then the input is replaced with the default qnan.
> * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
> gener
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> /*
> + * Vector unit-stride, strided, unit-stride segment, strided segment
> + * store check function.
> + *
> + * Rules to be checked here:
> + * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
> + * 2. Destination vector regi
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
> +uint8_t eew)
> {
> -return !s->vill;
> +uint8_t lmul_r = s->lmul < 0 ? 0 : s->lmul;
> +int8_t emul = ctzl(eew) - (s->sew + 3
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Replace ETYPE from signed int to unsigned int to prevent index overflow
> issue, which would lead to wrong index address.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/vector_helper.c | 8
> 1 file changed
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/helper.h | 27 +++-
> target/riscv/insn32.decode | 14 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 31 --
> target
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +static bool vext_check_amo(DisasContext *s, int vd, int vs2,
> + int wd, int vm, uint8_t eew)
> +{
> +int8_t emul = ctzl(eew) - (s->sew + 3) + s->lmul;
> +bool ret = has_ext(s, RVA) &&
> + (1 << s->
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +/*
> + * load and store whole register instructions ignore vtype and vl setting.
> + * Thus, we don't need to check vill bit. (Section 7.9)
> + */
> +#define GEN_LDST_WHOLE_TRANS(NAME, EEW, ARGTYPE, ARG_NF, IS_STORE) \
> +static bool trans_##
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +static uint8_t vext_get_emul(DisasContext *s, uint8_t eew)
> +{
> +int8_t emul = ctzl(eew) - (s->sew + 3) + s->lmul;
> +return emul < 0 ? 0 : emul;
> +}
Same comment about EEW being encoded as MemOp to match SEW.
r~
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
> calculation for RVV 1.0.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/cpu.h | 43 ++---
> target/riscv/in
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
> +{
> +int8_t emul = 4 - (s->sew + 3) + s->lmul;
Similarly for EEW elsewhere. This should be
int emul = MO_16 - s->sew + s->lmul;
> @@ -3339,7 +3353,8 @@ static bool tra
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> {
> if (require_rvv(s) &&
> +has_ext(s, RVF) &&
> vext_check_isa_ill(s) &&
> require_align(a->rd, 1 << s->lmul) &&
> (s->sew != 0)) {
> +
On 8/29/20 1:00 PM, Richard Henderson wrote:
> static bool require_rvf(Disascontext *s)
> {
> switch (s->sew) {
> case MO_16:
> case MO_32:
> return has_ext(s, RVF);
> case MO_64:
> return has_ext(s, RVD);
> default:
> return false;
> }
> }
Oh, and c
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn32.decode | 4 +--
> target/riscv/insn_trans/trans_rvv.inc.c | 42 +
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Add the following instructions:
>
> * vmv1r.v
> * vmv2r.v
> * vmv4r.v
> * vmv8r.v
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn32.decode | 4
> target/riscv/insn_trans/trans_rvv.inc.c | 25
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Add the following instructions:
>
> * vaaddu.vv
> * vaaddu.vx
> * vasubu.vv
> * vasubu.vx
>
> Remove the following instructions:
>
> * vadd.vi
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/helper.h
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Clear tail elements only if VTA is agnostic.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn32.decode | 20 ++--
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> target/riscv/vec
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/translate.c | 2 ++
> 3 files changed, 4 insertions(+)
Reviewed-by: Richard Henderson
r~
On 8/29/20 1:17 PM, Richard Henderson wrote:
> On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
>> From: Frank Chang
>>
>> Signed-off-by: Frank Chang
>> ---
>> target/riscv/cpu.c | 1 +
>> target/riscv/cpu.h | 1 +
>> target/riscv/translate.c | 2 ++
>> 3 files changed, 4 insertions
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Sign-extend vsaddu.vi immediate value.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Add the following instructions:
>
> * vqmaccu.vv
> * vqmaccu.vx
> * vqmacc.vv
> * vqmacc.vx
> * vqmaccsu.vv
> * vqmaccsu.vx
> * vqmaccus.vx
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/helper.h
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> * Sign-extend vmselu.vi and vmsgtu.vi immediate values.
> * Remove "set tail elements to zeros" as tail elements can be unchanged
> for either VTA to have undisturbed or agnostic setting.
>
> Signed-off-by: Frank Chang
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/vector_helper.c | 8
> 1 file changed, 8 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
> target/riscv/vector_helper.c| 4
> 2 files changed, 2 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> * Remove clear function from helper functions as the tail elements
> are unchanged in RVV 1.0.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/vector_helper.c | 19 ---
> 1 file changed, 12 insertio
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfslide1down_vf_h, void, p
Hello,
On Sat, 29 Aug 2020 18:45:06 +0200
Philippe Mathieu-Daudé wrote:
> > > > However the NetBSD revision 1.32 of the driver introduced
> > > > 64-bit accesses to the stippler and blitter [2]. It is safe
> > > > to assume these memory regions are 64-bit accessible.
> > > > QEMU implementation
Host CPU : Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz
Host Memory : 15.49 GB
Start Time (UTC) : 2020-08-29 22:35:01
End Time (UTC) : 2020-08-29 23:07:59
Execution Time : 0:32:57.786998
Status : SUCCESS
Note:
Changes denoted by '-' are less than 0.01%.
-
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/vector_helper.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
The one sentence in the manual is quite poor for this, and needs improvement:
> Floati
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> log(SEW) truncate vssra.vi immediate value.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/29/20 4:50 PM, Richard Henderson wrote:
> It doesn't actually say anything about the way in which we've implemented the
> *_noprop functions.
Ho hum. It seems v2.2 has changed fmin/fmax for the fpu as well.
We really should fix that too...
r~
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/vector_helper.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/fpu_helper.c | 12 ++--
> target/riscv/insn_trans/trans_rvv.inc.c | 18 +-
> target/riscv/internals.h| 9 +
>
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +DEF_HELPER_5(vfcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfcvt_rtz_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfcvt_rtz_x_f_v_h, void, ptr, pt
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> @@ -995,12 +995,18 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env,
> i32)
> DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vfwcvt_x_f_v_w, vo
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
> should be an interface private to translation, so add a new independent
> helper_set_rod_rounding_mode().
>
> Signed-off-by: Frank Chang
> ---
>
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +DEF_HELPER_5(vfncvt_rod_f_f_w_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_rod_f_f_w_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_rtz_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_rtz_xu_f_w_h, void, ptr,
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> As GVEC only supports MAXSZ and OPRSZ in the range of: [8..256] bytes
> and LMUL could be a fractional number. The maximum vector size can be
> operated might be less than 8 bytes or larger than 256 bytes.
> Skip to use GVE
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> +++ b/gdb-xml/riscv-64bit-csr.xml
> @@ -248,4 +248,11 @@
>
>
>
> +
> +
> +
> +
> +
> +
> +
Just because these are csr's doesn't mean they're unrelated to RVV. I would
think that ideally they would be in the (generated)
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Greentime Hu
>
> This patch adds vector support for rv32 gdb. It allows gdb client to access
> vector registers correctly.
>
> Signed-off-by: Greentime Hu
> Signed-off-by: Frank Chang
> ---
> gdb-xml/riscv-32bit-csr.xml | 7 +++
>
On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Hsiangkai Wang
>
> Signed-off-by: Hsiangkai Wang
> Signed-off-by: Frank Chang
> ---
> gdb-xml/riscv-32bit-csr.xml | 11 ++-
> gdb-xml/riscv-64bit-csr.xml | 11 ++-
> target/riscv/gdbstub.c | 4 ++--
> 3 files chang
gs/pull-sf-20200829
for you to fetch changes up to c53b1079334c41b342a8ad3b7ccfd51bf5427f5a:
softfloat: Define comparison operations for bfloat16 (2020-08-29 19:25:42
-0700)
* float16 comparison wrappers
* float16 conversions to/
From: Stephen Long
This float16 predicate was missing from the normal set.
Signed-off-by: Stephen Long
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 0a5a5e5d0b..863d
From: Kito Cheng
Implement them in softfloat and remove the local versions in riscv.
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Acked-by: Alex Bennée
Reviewed-by: Alistair Francis
Message-Id: <1596102747-20226-2-git-send-email-chihmin.c...@sifive.com>
Signed-off-by: Richard Hende
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 41 +
1 file changed, 41 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 1233f98014..78ad5ca738 100644
--- a/include/fpu/softfloat.h
From: Frank Chang
Reviewed-by: Alex Bennée
Signed-off-by: Frank Chang
Message-Id: <1596102747-20226-4-git-send-email-chihmin.c...@sifive.com>
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 8
fpu/softfloat.c | 34 ++
2 files ch
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200813071421.2509-3-zhiwei_...@c-sky.com>
[rth: Use FloatRoundMode for conversion functions.]
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 54 ++
fpu/softfloat.c | 223 +
From: LIU Zhiwei
This patch implements operations for bfloat16 except conversion and some misc
operations. We also add FloatFmt and pack/unpack interfaces for bfloat16.
As they are both static fields, we can't make a sperate patch for them.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henders
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200813071421.2509-4-zhiwei_...@c-sky.com>
[rth: Fix merge conflict with NO_SIGNALING_NANS; use bool for predicates.]
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h| 48 ++
On Sat, Aug 22, 2020 at 02:21:27PM -, Philippe Mathieu-Daudé wrote:
> The S24/TCX datasheet is listed as "Unable to locate" on [1].
>
> However the NetBSD revision 1.32 of the driver introduced
> 64-bit accesses to the stippler and blitter [2]. It is safe
> to assume these memory regions are
On Wed, Aug 26, 2020 at 10:32:16PM -0700, Nathan Chancellor wrote:
> Hi all,
>
> Sorry for the duplicate reply, my first one was rejected by a mailing
> list administrator for being too long so I resent it with the error logs
> as a link instead of inline.
>
> On Wed, Jun 10, 2020 at 09:47:49AM -
On Sun, Aug 30, 2020 at 02:20:38AM -0400, Michael S. Tsirkin wrote:
> On Wed, Aug 26, 2020 at 10:32:16PM -0700, Nathan Chancellor wrote:
> > Hi all,
> >
> > Sorry for the duplicate reply, my first one was rejected by a mailing
> > list administrator for being too long so I resent it with the error
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