On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote: > From: Hsiangkai Wang <kai.w...@sifive.com> > > Signed-off-by: Hsiangkai Wang <kai.w...@sifive.com> > Signed-off-by: Frank Chang <frank.ch...@sifive.com> > --- > gdb-xml/riscv-32bit-csr.xml | 11 ++++++----- > gdb-xml/riscv-64bit-csr.xml | 11 ++++++----- > target/riscv/gdbstub.c | 4 ++-- > 3 files changed, 14 insertions(+), 12 deletions(-)
Looks ok, from a quick glance. I do think that this could stand to be auto-generated as well, from an extended csr_ops table. Extended in that you'd want to include the name and the isa bit to which the register applies. I'll let Alistair weigh in on this. But either way, Acked-by: Richard Henderson <richard.hender...@linaro.org> r~
