On 11/02/2019 15:56, Alexey Kardashevskiy wrote:
>
>
> On 09/02/2019 04:26, Paolo Bonzini wrote:
>> On 07/02/19 12:49, Dr. David Alan Gilbert wrote:
>>> //#define DEBUG_UNASSIGNED
>>> @@ -2924,6 +2926,8 @@ struct FlatViewInfo {
>>> int counter;
>>> bool dispatch_tree;
>>> bool
On 18/03/2019 18:05, Alberto Garcia wrote:
> On Thu 21 Feb 2019 04:26:38 PM CET, Andrey Shinkevich wrote:
>> The test case TestParallelOps::test_stream_parallel in #030 fails
>> if a base node is protected by the block-stream running job that
>> includes the base node into the job node list (bloc
On 19/03/2019 01:18, John Snow wrote:
>
>
> On 2/28/19 4:26 AM, Andrey Shinkevich wrote:
>> When a bitmap is removed, we can clean some space on the disk. The size
>> of a cluster may be larger, so is the size of the bitmap that includes
>> many clusters. Some bitmaps can be as large as tens of
Fixes: b93b63f574c "test makefile overhaul"
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
Posted long ago as part of an RFC series that got stuck due to lack of
time. Rebased.
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makef
Thanks Yury.
On 2019/3/14 19:03, Yury Kotov wrote:
This patch isn't intended to merge. Just to reproduce a problem.
The test for x-ignore-shread capability fails on aarch64 + tcg:
Memory content inconsistency at 44c0 first_byte = 2 last_byte = 1 current =
d1 hit_edge = 1
Memory content inc
Control-flow Enforcement Technology (CET) provides protection against
return/jump-oriented programming (ROP) attacks. To make kvm Guest OS own
the capability, this patch-set is required. It enables CET related CPUID
report, xsaves/xrstors and live-migration etc. in Qemu.
Changelog:
v4:
- Added M
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386/c
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f6c7bdf6fe..11dbb9bcc4 1
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 33 -
1 file changed, 32 insert
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386/cp
To support features such as live-migration,
CET runtime MSRs need to be saved in source machine and
restored on destination machine, this patch is to save
and restore CET_U, CET_S, PL0_SSP/PL1_SSP/PL2_SSP/PL3_SSP
and SSP_TABL_ADDR MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 1
On Tue, 19 Mar 2019 08:45:23 +0800
Wei Yang wrote:
> On Mon, Mar 18, 2019 at 01:39:12PM +0100, Igor Mammedov wrote:
> >On Fri, 15 Mar 2019 08:44:32 +0800
> >Wei Yang wrote:
> >
> >in subject: s/extract/generalize/
> >
> >> arm and i386 has almost the same function acpi_add_rom_blob(), except
>
Am 18.03.2019 um 18:21 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 18.03.2019 um 17:03 hat Markus Armbruster geschrieben:
> >> Kevin Wolf writes:
> >>
> >> > Am 08.03.2019 um 18:03 hat Markus Armbruster geschrieben:
> >> >> >> bool blk_check_size_and_read_all(BlockBackend *
On 18.3.19. 19:30, Peter Maydell wrote:
On Mon, 18 Mar 2019 at 18:26, Mateja Marjanovic
wrote:
From: Mateja Marjanovic
Wrong type of NaN was generated for IEEE754-2008 by maddf and
msubf insturctions when the arguments were inf, zero, nan or
zero, inf, nan respectively.
Signed-off-by: Mate
On 18.3.19. 19:55, Aleksandar Markovic wrote:
Hi, Mateja,
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Fix minor bug in FPU
From: Mateja Marjanovic
Wrong type of NaN was generated for IEEE754-2008 by maddf and
msubf insturctions when the arguments were inf, zero, nan or
zero, inf
On Mon, 18 Mar 2019 at 21:21, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> Le dim. 17 mars 2019 23:02, Peter Maydell a écrit :
>>
>> On Sun, 17 Mar 2019 at 20:29, Peter Maydell wrote:
>> > Hi; this fails to build on OSX and OpenBSD:
>> >
>> > UNXZpc-bios/edk2-aarch64-code.fd.xz
>> > /bi
On 18.3.19. 20:08, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Fix minor bug in FPU
From: Mateja Marjanovic
Wrong type of NaN was generated for IEEE754-2008 by maddf and
msubf insturctions when the arguments were inf, zero, nan or
zero, inf, nan respecti
Job (especially mirror) may call block_job_error_action several
times before actual pause if it has several in-flight requests.
block_job_error_action will call job_pause more than once in this case,
which lead to following block-job-resume qmp command can't actually
resume the job.
Fix it by do
On Tue, 19 Mar 2019 at 07:36, Jia He wrote:
>
> Thanks Yury.
>
> On 2019/3/14 19:03, Yury Kotov wrote:
> > This patch isn't intended to merge. Just to reproduce a problem.
> >
> > The test for x-ignore-shread capability fails on aarch64 + tcg:
> > Memory content inconsistency at 44c0 first_byt
On 18.3.19. 20:42, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Fix minor bug in FPU
"v2" is missing in the subject line, and now v1 and v2 are incorrectly
linked on mailing list website.
I accidentally forgot to add v2 in the subject line.
An isolated p
On Mon, Mar 18, 2019 at 04:11:21PM -0300, Eduardo Habkost wrote:
> On Tue, Mar 12, 2019 at 09:19:37PM -0400, Michael S. Tsirkin wrote:
> > On Fri, Feb 15, 2019 at 10:32:37AM +, Daniel P. Berrangé wrote:
> > > Changed in v2:
> > >
> > > - Fix properties set for v2.6 machine type compat so that
On 2019/3/18 20:49, Peter Maydell wrote:
> On Mon, 18 Mar 2019 at 12:34, gengdongjiu wrote:
>>
>>
>>
>> On 2019/3/16 4:11, Philippe Mathieu-Daudé wrote:
Signed-off-by: Peter Maydell
---
Should we try to put this in for rc1? Not sure... Testing
definitely appreciated.
>>> You m
On Mon, Mar 18, 2019 at 07:33:12PM +0100, Markus Armbruster wrote:
> We blame badness in positional arguments on the last option argument:
>
> $ qemu-system-x86_64 -vnc :1 bad.img
> qemu-system-x86_64: -vnc :1: Could not open 'foo': No such file or
> directory
>
> I believe we've done th
On Tue, Mar 19, 2019 at 09:51:19AM +0530, Sarah Abraham wrote:
> Hey all!
> I am Sarah Abraham and I'm an Outreachy applicant for May '19-Aug '19
> round.I'm really interested to work on the project "Improve GNOME boxes
> express-installations by adding support to tree-based installations" .
>
* Yury Kotov (yury-ko...@yandex-team.ru) wrote:
> This patch isn't intended to merge. Just to reproduce a problem.
>
> The test for x-ignore-shread capability fails on aarch64 + tcg:
> Memory content inconsistency at 44c0 first_byte = 2 last_byte = 1 current
> = d1 hit_edge = 1
> Memory conte
Hi Stefan,
After more detail test, I found two results:
1) This route entry's lost can be reproduced on both virtio-net and
pass-through physical devices.
2) The link down event is handled by a service named NetworkManager in my VM
(CentOS linux 3.10.0-514-e17.x86_64). If I stop or kill this s
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 19 Mar 2019 at 07:36, Jia He wrote:
> >
> > Thanks Yury.
> >
> > On 2019/3/14 19:03, Yury Kotov wrote:
> > > This patch isn't intended to merge. Just to reproduce a problem.
> > >
> > > The test for x-ignore-shread capability fails on aar
176dccee "target/ppc/spapr: Clear partition table entry when allocating
hash table" reworked the H_REGISTER_PROCESS_TABLE hypercall, but
unfortunately due to a small error no longer correctly sets the LPCR[GTSE]
bit which allows the guest to directly execute (some types of) tlbie (TLB
flush) instru
From: Markus Armbruster
Patch created mechanically by rerunning:
$ spatch --sp-file scripts/coccinelle/error_propagate_null.cocci \
--macro-file scripts/cocci-macro-file.h \
--dir . --in-place
Signed-off-by: Markus Armbruster
Message-Id: <20190318190148.18283-1-arm..
The following changes since commit 082c0543baa6f237704c83a51658bd7f6ae316d5:
scripts/make-release: Stop shipping u-boot source as a tarball (2019-03-18
15:40:00 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20190319
for you to fetch
From: Greg Kurz
Detected by Coverity: CID 1399702
Signed-off-by: Greg Kurz
Message-Id: <155248884129.893204.2293309859485638162.st...@bahia.lan>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/p
From: Benjamin Herrenschmidt
H_IPOLL takes the CPU# of the processor to poll as an argument,
it doesn't operate on self.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Message-Id: <20190314063855.27890-1-...@kaod.org>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
From: Greg Kurz
PSI registers are 64-bit.
Spotted by Coverity: CID 1399704
Signed-off-by: Greg Kurz
Message-Id: <155248884690.893204.5428179144527749023.st...@bahia.lan>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv_psi.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Cédric Le Goater
and declare David and myself as maintainers of the PPC PowerNV
(Non-Virtualized) machine using the OPAL (skiboot) firmware.
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Message-Id: <20190313162423.22081-1-...@kaod.org>
Signed-off-by: David Gibson
---
MAINTAIN
Richard Henderson writes:
> On 3/18/19 12:46 PM, Peter Maydell wrote:
>> Hi; for the M-profile floating point work I'm going to need I think
>> three new TB flags (to control whether to generate the code to do
>> the various independent things the pseudocode ExecuteFPCheck() function
>> does be
Kevin Wolf writes:
> Am 18.03.2019 um 18:21 hat Markus Armbruster geschrieben:
>> Kevin Wolf writes:
>>
>> > Am 18.03.2019 um 17:03 hat Markus Armbruster geschrieben:
>> >> Kevin Wolf writes:
>> >>
>> >> > Am 08.03.2019 um 18:03 hat Markus Armbruster geschrieben:
>> >> >> >> bool blk_check_si
ping
On Thu, Mar 07, 2019 at 12:18:36PM +, Daniel P. Berrangé wrote:
> This corrects the note about spec-ctrl and adds info about the stibp
> flag that was later added to QEMU/KVM.
>
> Daniel P. Berrangé (2):
> docs: clarify that spec-ctrl is only needed for Spectre v2
> docs: add note ab
Am 19.03.2019 um 11:34 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 18.03.2019 um 18:21 hat Markus Armbruster geschrieben:
> >> Kevin Wolf writes:
> >>
> >> > Am 18.03.2019 um 17:03 hat Markus Armbruster geschrieben:
> >> >> Kevin Wolf writes:
> >> >>
> >> >> > Am 08.03.20
On Tue, 19 Mar 2019 at 09:40, Dr. David Alan Gilbert
wrote:
> I thought that ROMs would either:
>a) Be mapped shared from a file but then read-only and unwritten
I don't think we support this at all, do we?
> or
>b) Be written to during boot - but this wouldn't be main memory, so
> would
On Mon, 18 Mar 2019 at 16:24, Michael Roth wrote:
>
> The following changes since commit 3c18a08cf387d44a351b9877497b5e0ea27c5140:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/seabios-1.12.1-20190318-pull-request' into staging
> (2019-03-18 13:14:24 +)
>
> are available in the G
19.03.2019, 12:39, "Dr. David Alan Gilbert" :
> * Yury Kotov (yury-ko...@yandex-team.ru) wrote:
>> This patch isn't intended to merge. Just to reproduce a problem.
>>
>> The test for x-ignore-shread capability fails on aarch64 + tcg:
>> Memory content inconsistency at 44c0 first_byte = 2 las
Am 19.03.2019 um 10:24 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Job (especially mirror) may call block_job_error_action several
> times before actual pause if it has several in-flight requests.
>
> block_job_error_action will call job_pause more than once in this case,
> which lead to follo
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 19 Mar 2019 at 09:40, Dr. David Alan Gilbert
> wrote:
> > I thought that ROMs would either:
> >a) Be mapped shared from a file but then read-only and unwritten
>
> I don't think we support this at all, do we?
OK, I thought we did so
Unless overridden via an env var or configure arg, QEMU will only look
for the 'python' binary in $PATH. This is unhelpful on distros which
are only shipping Python 3.x (eg Fedora) in their default install as,
if they comply with PEP 394, the bare 'python' binary won't exist.
This changes configur
Am 18.03.2019 um 16:48 hat Alberto Garcia geschrieben:
> Signed-off-by: Alberto Garcia
Thanks, applied to the block branch.
Kevin
On Mon, 18 Mar 2019 at 23:36, Richard Henderson
wrote:
>
> On 3/18/19 12:46 PM, Peter Maydell wrote:
> > Hi; for the M-profile floating point work I'm going to need I think
> > three new TB flags (to control whether to generate the code to do
> > the various independent things the pseudocode Execu
On Tue, 19 Mar 2019 at 11:03, Dr. David Alan Gilbert
wrote:
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > I didn't think migration distinguished between "main memory"
> > and any other kind of RAMBlock-backed memory ?
>
> In Yury's case there's a distinction between RAMBlock's that are
ping
On Thu, Mar 07, 2019 at 04:58:24PM +, Daniel P. Berrangé wrote:
> We were never reporting the G_IO_HUP event when an end of file was hit
> on the websocket channel.
>
> We also didn't report G_IO_ERR when we hit a fatal error processing the
> websocket protocol.
>
> The latter in partic
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD, using directly
tcg registers and performing logic on them instead of
using helpers.
instr|| before|| after
==
ilvod.b || 117.50 ms || 24.99 ms
ilvod.h || 93.16 ms || 24.27
From: Mateja Marjanovic
Optimize MSA instructions ILVEV. and ILVOD.,
using directly tcg registers and performing logic on
them insted of using helpers. Reduce the number of logic
operations to a minimum, add comments and clean up
some typing errors.
Mateja Marjanovic (2):
target/mips: Optimize
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV, using directly
tcg registers and performing logic on them instead of
using helpers.
instr|| before|| after
==
ilvev.b || 126.92 ms || 26.41 ms
ilvev.h || 93.67 ms || 25.79
On Fri, 15 Mar 2019 11:33:09 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Mar 15, 2019 at 6:45 AM Chih-Min Chao wrote:
This is the 5th version of the patch set, based on the Jim's previous work,
http://lists.nongnu.org/archive/html/qemu-riscv/2019-02/msg00059.html
v4 -> v5:
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 19 Mar 2019 at 11:03, Dr. David Alan Gilbert
> wrote:
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > I didn't think migration distinguished between "main memory"
> > > and any other kind of RAMBlock-backed memory ?
> >
>
On Tue, 19 Mar 2019 at 11:45, Palmer Dabbelt wrote:
> This is another one that got queued up behind the decode tree stuff. I'd call
> this a new feature, but give that it's been on the list and reviewed I'm not
> sure if it's OK for master right now.
>
> Peter: is this too much of a change for po
On Tue, 19 Mar 2019 04:55:18 PDT (-0700), Peter Maydell wrote:
On Tue, 19 Mar 2019 at 11:45, Palmer Dabbelt wrote:
This is another one that got queued up behind the decode tree stuff. I'd call
this a new feature, but give that it's been on the list and reviewed I'm not
sure if it's OK for mast
On Mon, Mar 18, 2019 at 07:33:12PM +0100, Markus Armbruster wrote:
> We blame badness in positional arguments on the last option argument:
>
> $ qemu-system-x86_64 -vnc :1 bad.img
> qemu-system-x86_64: -vnc :1: Could not open 'foo': No such file or
> directory
>
> I believe we've done th
The Cascadelake-Server CPU was added last year in
commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8
Author: Tao Xu
Date: Wed Sep 19 11:11:22 2018 +0800
i386: Add new model of Cascadelake-Server
The commit message says that MSR based features are initially
omitted from its definition:
On Thu, Mar 07, 2019 at 04:58:24PM +, Daniel P. Berrangé wrote:
> We were never reporting the G_IO_HUP event when an end of file was hit
> on the websocket channel.
>
> We also didn't report G_IO_ERR when we hit a fatal error processing the
> websocket protocol.
>
> The latter in particular m
On Sun, 10 Feb 2019 12:17:26 PST (-0800), lukas.a...@aisec.fraunhofer.de wrote:
Re-add the previous compatible string "riscv-virtio-soc" to the soc
device tree node to allow U-Boot and Linux to bind machine-specific
drivers to it. The current compatible string "simple-bus" is retained.
This is r
On Tue, 2019-03-19 at 05:19 -0700, Palmer Dabbelt wrote:
> On Sun, 10 Feb 2019 12:17:26 PST (-0800),
> lukas.a...@aisec.fraunhofer.de wrote:
> > Re-add the previous compatible string "riscv-virtio-soc" to the soc
> > device tree node to allow U-Boot and Linux to bind machine-specific
> > drivers t
On 18/03/19 14:40, Peter Maydell wrote:
Normally configure identifies the source path by looking
at the location where the configure script itself exists.
We also provide a --source-path option which lets the user
manually override this.
There isn't really an obvious use case for the --source-pa
gt;
> git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20190319
>
> for you to fetch changes up to e366d181ceb96109b3f4fc6f8356bea644117f9a:
>
> spapr: Remove NULL checks on error_propagate() calls (2019-03-19 15:24:15
> +1100)
>
> --
> From: Mateja Marjanovic
> Subject: [PATCH 0/2] target/mips: Optimize MSA ILVEV and ILVOD instructions
Always use full instruction names, possibly shortened using Backus-Naur forms.
Series version again missing.
>
> From: Mateja Marjanovic
>
> Optimize MSA instructions ILVEV. and ILVOD.,
>
On Tue, 19 Mar 2019 11:52:45 +
"Dr. David Alan Gilbert" wrote:
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Tue, 19 Mar 2019 at 11:03, Dr. David Alan Gilbert
> > wrote:
> > >
> > > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > > I didn't think migration distinguis
From: Michael Clark
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Richard Henderson
Cc: Alistair Francis
Reviewed-by: Laurent Vivier
Signed-off-by: Michael Clark
Signed-off-by: Alistair F
From: Bin Meng
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
From: Bin Meng
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/
On Thu, 7 Mar 2019 10:07:05 +
Daniel P. Berrangé wrote:
> On Wed, Mar 06, 2019 at 07:54:17PM +0100, Igor Mammedov wrote:
> > On Wed, 6 Mar 2019 18:16:08 +
> > Daniel P. Berrangé wrote:
> >
> > > On Wed, Mar 06, 2019 at 06:33:25PM +0100, Igor Mammedov wrote:
> > > > Amend -numa optio
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index feea169e1223..d61bce6d5581 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820feaa..3199238ba01e 100644
--- a/hw/riscv/sifive_u.c
+++ b
From: Michael Clark
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.
Fixes WFI doesn't return when a IPI is issued:
- https://github.com/riscv/riscv-qemu/issues/132
To test:
1) App
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
Makefile.objs | 1 +
target/riscv/cpu_helper.c | 12 +++-
target/riscv/trace-events | 2 ++
3 files changed, 6 ins
From: Michael Clark
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:
pc = mtvec + cause * 4
In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync
From: Kito Cheng
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.
Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.
Cc: Palmer Dabbelt
Cc: Sagar Kara
From: Michael Clark
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dab
From: Michael Clark
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.
This logic was previo
From: Michael Clark
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off
From: Jim Wilson
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 47 +++
gdb-xml/riscv-32bit-csr.xml | 250
gdb-
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616bd..b11c4ae22fbc 100644
--- a/target/ris
From: Jim Wilson
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
configure | 1 +
gdb-xml/riscv-32bit-fpu.xml | 6 +-
gdb-xml/riscv-64bit-cpu.xml | 47 +++
gdb-xml/riscv-64bit-csr.xml | 250
This is essentially a softmmu tweak so don't bother building
linux-user builds as well.
Signed-off-by: Alex Bennée
---
.travis.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
index 407fc25945..3fb3dab46e 100644
--- a/.travis.yml
+++ b/.travis.yml
From: Jim Wilson
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
notice:
The fpu xml from gdb 8.3 has unused register #, 65 and make fi
From: Jim Wilson
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Message-Id: <20190212230903.9215-1-j...@sifive.com>
Signed-off-by: Palmer Dabbelt
---
targ
The following changes since commit 86e2fca2d7f163c50b80254e0afdd4e16378b3bb:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190319' into
staging (2019-03-19 10:52:45 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags
On Tue, 19 Mar 2019 at 12:42, Igor Mammedov wrote:
> on aarch(64) we also load dtb into main RAM currently only on boot,
Hmm? We load the DTB in hw/arm/boot.c using rom_add_blob_fixed_as(),
which means that it will use this "rom blob loading" mechanism,
so it should be re-copied into RAM on reset
From: Jim Wilson
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Message-Id: <20190212230830.9160-1-j...@sifive.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35
We define a new class of targets (MAIN_SOFTMMU_TARGETS) to cover the
major architectures. We either just build those or use the new
target-list-exclude mechanism to remove them from the list. This will
hopefully stop some of the longer builds hitting the Travis timeout
limit.
Signed-off-by: Alex B
> From: Mateja Marjanovic
> Subject: Re: [PATCH] target/mips: Fix minor bug in FPU
>
>
> On 18.3.19. 20:08, Aleksandar Markovic wrote:
> >> From: Mateja Marjanovic
> >> Subject: [PATCH] target/mips: Fix minor bug in FPU
> >>
> >> From: Mateja Marjanovic
> >>
> >> Wrong type of NaN was generate
Kevin Wolf writes:
> Am 19.03.2019 um 11:34 hat Markus Armbruster geschrieben:
>> Kevin Wolf writes:
>>
>> > Am 18.03.2019 um 18:21 hat Markus Armbruster geschrieben:
[...]
>> >> Given the sad state of location tracking, I'm afraid we do need to map
>> >> from BlockBackend to some text that hel
This is an inverse selection which excludes a selected set of targets
from the default target list. It will mostly be useful for CI
configurations but it might be useful for some users as well.
You cannot specify --target-list and --target-list-exclude at the same
time.
Signed-off-by: Alex Bennée
Hi,
This is a fixup patch for 4.0 to help reduce the number of timeouts we
are seeing on Travis. We introduce a new way to slice the target list
and then use that to split up a few of the builds that are getting
close to the time limit.
Alex Bennée (3):
configure: add --target-list-exclude
Am 13.02.2019 um 23:53 hat Max Reitz geschrieben:
> The commit and mirror block nodes are filters, so they should be marked
> as such.
>
> Signed-off-by: Max Reitz
> Reviewed-by: Alberto Garcia
Then we need to update the definition of a filter:
/* set to true if the BlockDriver is a block
On Tue, 19 Mar 2019 12:53:49 +
Peter Maydell wrote:
> On Tue, 19 Mar 2019 at 12:42, Igor Mammedov wrote:
> > on aarch(64) we also load dtb into main RAM currently only on boot,
>
> Hmm? We load the DTB in hw/arm/boot.c using rom_add_blob_fixed_as(),
> which means that it will use this "ro
Am 13.02.2019 um 23:53 hat Max Reitz geschrieben:
> There is no reason why the constraints we put on @replaces should be
> limited to drive-mirror. Therefore, move the sanity checks from
> qmp_drive_mirror() to blockdev_mirror_common() so they apply to
> blockdev-mirror as well.
>
> Signed-off-by
> From: Mateja Marjanovic
> Sent: Tuesday, March 19, 2019 12:28 PM
> To: qemu-devel@nongnu.org
> Cc: aurel...@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
> Subject: [PATCH 1/2] target/mips: Optimize ILVOD. MSA instructions
>
> From: Mateja Marjanovic
>
> Optimize set of MSA instructions
> From: Mateja Marjanovic
> Subject: [PATCH 2/2] target/mips: Optimize ILVEV. MSA instructions
>
> ...
>
> +static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
> + uint32_t ws, uint32_t wt)
> +{
> +tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
Am 19.03.2019 um 14:25 hat Markus Armbruster geschrieben:
> >> > Maybe we want a BlockBackend level function that returns the
> >> > BlockBackend name if it isn't empty, and the root node name otherwise?
> >>
> >> Makes sense to me.
> >>
> >> What about calling it blk_name()? ;-P
> >>
> >> This
On Mon, Mar 18, 2019 at 10:43:12PM +0100, Marek Marczykowski-Górecki wrote:
> On Mon, Mar 18, 2019 at 06:37:31PM +0100, Roger Pau Monne wrote:
> > Or if it's not possible to honor the hinted address an error is returned
> > instead.
>
> Just to be sure: MAP_FIXED will cause to map at specified ad
On Sun, 10 Mar 2019 11:14:08 +0100
Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Mon, Mar 04, 2019 at 12:45:14PM +0100, Markus Armbruster wrote:
> >> Daniel P. Berrangé writes:
> >>
> >> > On Mon, Mar 04, 2019 at 08:13:53AM +0100, Markus Armbruster wrote:
> >> >> If we
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