The following changes since commit 86e2fca2d7f163c50b80254e0afdd4e16378b3bb:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190319' into
staging (2019-03-19 10:52:45 +0000)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc0-2
for you to fetch changes up to a9ec1c76d57491602b4d3b521f898905825ca848:
riscv: sifive_u: Correct UART0's IRQ in the device tree (2019-03-19 05:18:42
-0700)
----------------------------------------------------------------
RISC-V Patches for 4.0-rc0, Part 2
This patch set contains three major sources of bug fixes:
* Jim has added support for GDB XML files, as well as fixing access to
CSRs via the GDB stub.
* Alistair has rebased a large set of fixes from Michael that were still
in his patch queue. These fix bugs all over our tree, including:
* Logging of PMP errors.
* User ABI cleanups and fixes, most notably on RVE guests.
* Fixes for interrupt emulation fidelity.
* Improvements to the emulation fidelity of the sifive_u machine.
* Bin Meng has improved the emulation fidelity of the SiFive UART, which
now supports both TX and RX interrupts (as well as setting the correct
interrupt line).
This should clear out the bug fix queue that piled up after the
decodetree conversion.
----------------------------------------------------------------
Alistair Francis (3):
riscv: pmp: Log pmp access errors as guest errors
riscv: sifive_u: Allow up to 4 CPUs to be created
target/riscv: Remove unused struct
Bin Meng (2):
riscv: sifive_uart: Generate TX interrupt
riscv: sifive_u: Correct UART0's IRQ in the device tree
Jim Wilson (5):
RISC-V: Add 32-bit gdb xml files.
RISC-V: Add 64-bit gdb xml files.
RISC-V: Fixes to CSR_* register macros.
RISC-V: Add debug support for accessing CSRs.
RISC-V: Add hooks to use the gdb xml files.
Kito Cheng (1):
RISC-V: linux-user support for RVE ABI
Michael Clark (8):
RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
RISC-V: Allow interrupt controllers to claim interrupts
RISC-V: Remove unnecessary disassembler constraints
elf: Add RISC-V PSABI ELF header defines
RISC-V: Change local interrupts from edge to level
RISC-V: Add support for vectored interrupts
RISC-V: Convert trap debugging to trace events
RISC-V: Update load reservation comment in do_interrupt
Makefile.objs | 1 +
configure | 2 +
disas/riscv.c | 138 -----------------
gdb-xml/riscv-32bit-cpu.xml | 47 ++++++
gdb-xml/riscv-32bit-csr.xml | 250 +++++++++++++++++++++++++++++++
gdb-xml/riscv-32bit-fpu.xml | 50 +++++++
gdb-xml/riscv-64bit-cpu.xml | 47 ++++++
gdb-xml/riscv-64bit-csr.xml | 250 +++++++++++++++++++++++++++++++
gdb-xml/riscv-64bit-fpu.xml | 56 +++++++
hw/riscv/sifive_plic.c | 19 ++-
hw/riscv/sifive_u.c | 7 +-
hw/riscv/sifive_uart.c | 4 +-
include/elf.h | 10 ++
linux-user/riscv/cpu_loop.c | 15 +-
target/riscv/cpu.c | 15 +-
target/riscv/cpu.h | 13 ++
target/riscv/cpu_bits.h | 35 ++++-
target/riscv/cpu_helper.c | 168 +++++++++------------
target/riscv/cpu_user.h | 3 +-
target/riscv/csr.c | 54 ++++---
target/riscv/gdbstub.c | 350 ++++++++++++++++++++++++++++++++++++++++++--
target/riscv/pmp.c | 20 ++-
target/riscv/trace-events | 2 +
23 files changed, 1266 insertions(+), 290 deletions(-)
create mode 100644 gdb-xml/riscv-32bit-cpu.xml
create mode 100644 gdb-xml/riscv-32bit-csr.xml
create mode 100644 gdb-xml/riscv-32bit-fpu.xml
create mode 100644 gdb-xml/riscv-64bit-cpu.xml
create mode 100644 gdb-xml/riscv-64bit-csr.xml
create mode 100644 gdb-xml/riscv-64bit-fpu.xml
create mode 100644 target/riscv/trace-events
