** Also affects: debian
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/1329956
Title:
multi-core FreeBSD guest hangs after warm reboot
Status in QEMU:
* Halil Pasic [2017-11-08 17:54:20 +0100]:
Hi Halil,
> Add a fake device meant for testing the correctness of our css emulation.
>
> What we currently have is writing a Fibonacci sequence of uint32_t to the
> device via ccw write. The write is going to fail if it ain't a Fibonacci
> and indicat
I'm able to reproduce this issue, but using latest debian 9.
Debian 9
qemu version: 1:2.8+dfsg-6+deb9u3
kernel version: Linux vm2 4.9.0-3-amd64 #1 SMP Debian 4.9.30-2+deb9u5
(2017-09-19) x86_64 GNU/Linux
I'm attempting to cold boot, or warm reboot, pfsense 2.4.2 amd64 iso
image guest. If I have
sorry, make that https://redmine.pfsense.org/issues/4377
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https://bugs.launchpad.net/bugs/1329956
Title:
multi-core FreeBSD guest hangs after warm reboot
Status in QEMU:
Fix Release
I found this bug report through https://redmine.pfsense.org/issues/7925
, btw.
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https://bugs.launchpad.net/bugs/1329956
Title:
multi-core FreeBSD guest hangs after warm reboot
Status
Since the commit 11808bb0c422134bf09119f4aa22c59b0ce84bf3 removed
the put_buffer callback and using an iovec based write handler instead,
the docs should be sync with the code too.
Signed-off-by: Jay Zhou
---
docs/devel/migration.txt | 31 ++-
1 file changed, 18 inser
On 22.11.2017 23:05, Pierre Morel wrote:
> There are two places where the same endianness conversion
> is done.
> Let's factor this out into a static function.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Yi Min Zhao
> ---
> hw/s390x/s390-pci-inst.c | 59
> +++
On 22.11.2017 23:05, Pierre Morel wrote:
> Enhance the fault detection, correction of the fault reporting.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Yi Min Zhao
> ---
> hw/s390x/s390-pci-inst.c | 39 ++-
> 1 file changed, 22 insertions(+), 17 deletions(-
On 21/11/2017 8:42 PM, Kevin Wolf wrote:
Am 15.11.2017 um 17:30 hat Max Reitz geschrieben:
On 2017-11-15 17:28, Anton Nefedov wrote:
On 15/11/2017 6:11 PM, Max Reitz wrote:
On 2017-11-14 11:16, Anton Nefedov wrote:
From: Pavel Butsykin
At the moment, qcow2_co_pwritev_compressed can proces
On 23/11/2017 03:55, Deepa Srinivasan wrote:
> I agree that passing in QEMUIOVector to blk_aio_ioctl() as a holder of
> the void* buffer used in blk_aio_ioctl_entry() is unnecessary. But, as
> Kevin noted, read and write were using the QEMUIOVector in BlkRwCo.
>
> To avoid changes to the callers o
I picked up Alexey's patch to fix pci address space names (which is
possibly lost on the list), and refactored cpu address spaces a bit
more. Now most of the address spaces (I believe some corner cases are
there) should have a valid and good name. I think this is pretty safe
even for 2.11, but I'
From: Alexey Kardashevskiy
This moves pci_dev->name initialization earlier so
pci_dev->bus_master_as could get a name instead of an empty string.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Peter Xu
---
hw/pci/pci.c | 2 +-
1
Normally we create an address space for that CPU and pass that address
space into the function. Let's just do it inside to unify address space
creations. It'll simplify my next patch to rename those address spaces.
Signed-off-by: Peter Xu
---
cpus.c | 5 +
exec.c
Renaming cpu address space names so that they won't be the same when
there are more than one.
Signed-off-by: Peter Xu
---
exec.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index b4abe75931..c6e4c20c8f 100644
--- a/exec.c
+++ b/exec.c
@@ -719,9 +719,12
On 22.11.2017 23:05, Pierre Morel wrote:
> Enhance the fault detection.
>
> Fixup the precedence to check the destination path existance
> before checking for the source accessibility.
>
> Add the maxstbl entry to both the Query PCI Function Group
> response and the PCIBusDevice structure.
>
> I
On 22.11.2017 23:05, Pierre Morel wrote:
> Let's move the memory region read from pcilg into a dedicated function.
> This allows us to prepare a later patch.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Yi Min Zhao
> ---
> hw/s390x/s390-pci-inst.c | 15 +++
> 1 file changed, 11 in
On 22.11.2017 23:05, Pierre Morel wrote:
> Let's move the memory region write from pcistg into a dedicated
> function.
> This allows us to prepare a later patch searching for subregions
> inside of the memory region.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Yi Min Zhao
> ---
> hw/s390x/s3
Am 23.11.2017 um 10:04 hat Anton Nefedov geschrieben:
>
>
> On 21/11/2017 8:42 PM, Kevin Wolf wrote:
> > Am 15.11.2017 um 17:30 hat Max Reitz geschrieben:
> > > On 2017-11-15 17:28, Anton Nefedov wrote:
> > > > On 15/11/2017 6:11 PM, Max Reitz wrote:
> > > > > On 2017-11-14 11:16, Anton Nefedov w
On Thu, 23 Nov 2017 09:48:41 +0100
Thomas Huth wrote:
> On 22.11.2017 23:05, Pierre Morel wrote:
> > There are two places where the same endianness conversion
> > is done.
> > Let's factor this out into a static function.
> >
> > Signed-off-by: Pierre Morel
> > Reviewed-by: Yi Min Zhao
> > ---
On 22 November 2017 at 20:22, Andrey Smirnov wrote:
> On Tue, Nov 21, 2017 at 9:31 AM, Peter Maydell
> wrote:
>> On 6 November 2017 at 15:47, Andrey Smirnov wrote:
>>> Frame truncation length, TRUNC_FL, is determined by the contents of
>>> ENET_FTRL register, so convert the code to use it inste
On 22 November 2017 at 20:43, Andrey Smirnov wrote:
> On Tue, Nov 21, 2017 at 10:02 AM, Peter Maydell
> wrote:
>> On 6 November 2017 at 15:47, Andrey Smirnov wrote:
>>> +/* Controller does not provide transfer-complete interrupt when not busy */
>>> +#define SDHCI_QUIRK_NO_BUSY_IRQBIT(14)
>>
On 22.11.2017 23:05, Pierre Morel wrote:
> When dispatching memory access to PCI BAR region, we must
> look for possible subregions, used by the PCI device to map
> different memory areas inside the same PCI BAR.
>
> Since the data offset we received is calculated starting at the
> region start ad
On Wed, 22 Nov 2017 23:05:29 +0100
Pierre Morel wrote:
> Enhance the fault detection, correction of the fault reporting.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Yi Min Zhao
> ---
> hw/s390x/s390-pci-inst.c | 39 ++-
> 1 file changed, 22 insertions(+)
On 23.11.2017 10:49, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 09:48:41 +0100
> Thomas Huth wrote:
>
>> On 22.11.2017 23:05, Pierre Morel wrote:
>>> There are two places where the same endianness conversion
>>> is done.
>>> Let's factor this out into a static function.
>>>
>>> Signed-off-by: Pie
On Mon, 13 Nov 2017 08:14:28 +0100
Thomas Huth wrote:
> By the way, before everybody now introduces "2.12" machine types ... is
> there already a consensus that the next version will be "2.12" ?
>
> A couple of months ago, we discussed that we could maybe do a 3.0 after
> 2.11, e.g. here:
>
>
On Thu, 23 Nov 2017 11:01:23 +0100
Thomas Huth wrote:
> On 23.11.2017 10:49, Cornelia Huck wrote:
> > On Thu, 23 Nov 2017 09:48:41 +0100
> > Thomas Huth wrote:
> >
> >> On 22.11.2017 23:05, Pierre Morel wrote:
> >>> There are two places where the same endianness conversion
> >>> is done.
>
On 23 November 2017 at 10:03, Cornelia Huck wrote:
> On Mon, 13 Nov 2017 08:14:28 +0100
> Thomas Huth wrote:
>
>> By the way, before everybody now introduces "2.12" machine types ... is
>> there already a consensus that the next version will be "2.12" ?
>>
>> A couple of months ago, we discussed
On Wed, Nov 22, 2017 at 07:04:26PM +0100, Kevin Wolf wrote:
> Am 22.11.2017 um 18:06 hat Stefan Hajnoczi geschrieben:
> > On Wed, Nov 22, 2017 at 07:33:28AM -0800, Deepa Srinivasan wrote:
> > > Starting qemu with the following arguments causes qemu to segfault:
> > > ... -device lsi,id=lsi0 -drive
On 23.11.2017 11:08, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 11:01:23 +0100
> Thomas Huth wrote:
>
>> On 23.11.2017 10:49, Cornelia Huck wrote:
>>> On Thu, 23 Nov 2017 09:48:41 +0100
>>> Thomas Huth wrote:
On 22.11.2017 23:05, Pierre Morel wrote:
[...]
> +/**
> + * Swap data co
On Thu, 23 Nov 2017 11:25:10 +0100
Thomas Huth wrote:
> On 23.11.2017 11:08, Cornelia Huck wrote:
> > On Thu, 23 Nov 2017 11:01:23 +0100
> > Thomas Huth wrote:
> >
> >> On 23.11.2017 10:49, Cornelia Huck wrote:
> >>> On Thu, 23 Nov 2017 09:48:41 +0100
> >>> Thomas Huth wrote:
> On 2
On 23/11/2017 11:23, Stefan Hajnoczi wrote:
> You are right. I audited the blk_aio_preadv() callers and they all keep
> qiov around until the request is complete.
>
> Actually this makes sense because even in the simple non-coroutine case
> with aio=threads the qiov hasn't necessarily been read y
On 22 November 2017 at 08:41, Juan Quintela wrote:
> This commit started use tb_unlock() and tlb_set_dirty() on non TCG
> code. Add the function as stubs.
>
> commit 27266271977c5a30f2f7d493e042be1897827bdd
> Author: Peter Maydell
> Date: Mon Nov 20 18:08:27 2017 +
>
> exec.c: Factor o
* Peter Xu (pet...@redhat.com) wrote:
> Create one IOThread for the monitors, prepared to handle all the
> input/output IOs using existing iothread framework.
>
> Signed-off-by: Peter Xu
> ---
> monitor.c | 29 +
> 1 file changed, 29 insertions(+)
>
> diff --git a/mo
* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > Create one IOThread for the monitors, prepared to handle all the
> > input/output IOs using existing iothread framework.
> >
> > Signed-off-by: Peter Xu
> > ---
> > monitor.c | 29 ++
FOSDEM 2018 will be held in Brussels, Belgium on February 3 & 4, 2018.
The Virt & Iaas Devroom is hosting talks on KVM, Libvirt, QEMU,
OpenStack, and more.
The submission deadline for talks is 1 December 2017. See the Call
For Papers below for details.
I hope to see you there!
Stefan
---
I am e
On Thu, Nov 23, 2017 at 10:51:43AM +, Dr. David Alan Gilbert wrote:
> * Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
> > * Peter Xu (pet...@redhat.com) wrote:
> > > Create one IOThread for the monitors, prepared to handle all the
> > > input/output IOs using existing iothread framework.
On 23.11.2017 11:17, Peter Maydell wrote:
> On 23 November 2017 at 10:03, Cornelia Huck wrote:
>> On Mon, 13 Nov 2017 08:14:28 +0100
>> Thomas Huth wrote:
>>
>>> By the way, before everybody now introduces "2.12" machine types ... is
>>> there already a consensus that the next version will be "2.
On Thu, Nov 23, 2017 at 11:37:46AM +0800, Jason Wang wrote:
> Guest state should not be touched if VM is stopped, unfortunately we
> didn't check running state and tried to drain tx queue unconditionally
> in virtio_net_set_status(). A crash was then noticed as a migration
> destination when user t
On Thu, Nov 23, 2017 at 11:57:34AM +0100, Thomas Huth wrote:
> On 23.11.2017 11:17, Peter Maydell wrote:
> > On 23 November 2017 at 10:03, Cornelia Huck wrote:
> >> On Mon, 13 Nov 2017 08:14:28 +0100
> >> Thomas Huth wrote:
> >>
> >>> By the way, before everybody now introduces "2.12" machine typ
On Mon, Nov 20, 2017 at 01:07:42PM +0100, Greg Kurz wrote:
> On Fri, 17 Nov 2017 15:50:53 +1100
> David Gibson wrote:
>
> > On Tue, Nov 14, 2017 at 10:42:24AM +0100, Greg Kurz wrote:
> > > On Fri, 10 Nov 2017 15:20:11 +
> > > Cédric Le Goater wrote:
> > >
> > > > Let's define a new set of
On Fri, Nov 17, 2017 at 08:19:23AM +0100, Cédric Le Goater wrote:
> On 11/17/2017 05:50 AM, David Gibson wrote:
> > On Tue, Nov 14, 2017 at 10:42:24AM +0100, Greg Kurz wrote:
> >> On Fri, 10 Nov 2017 15:20:11 +
> >> Cédric Le Goater wrote:
> >>
> >>> Let's define a new set of XICSFabric IRQ op
On Fri, Nov 17, 2017 at 08:23:00AM +0100, Cédric Le Goater wrote:
> On 11/17/2017 05:54 AM, David Gibson wrote:
> > On Fri, Nov 10, 2017 at 03:20:14PM +, Cédric Le Goater wrote:
> >> It will be used later on to distinguish the allocation of an LSI
> >> interrupt from an MSI and also to reduce t
On Fri, Nov 17, 2017 at 08:16:47AM +0100, Cédric Le Goater wrote:
> On 11/17/2017 05:48 AM, David Gibson wrote:
> > On Fri, Nov 10, 2017 at 03:20:09PM +, Cédric Le Goater wrote:
> >> Currently, the ICSState 'ics' object of the sPAPR machine acts as the
> >> global interrupt source handler and a
On Thu, Nov 23, 2017 at 10:17:48AM +, Peter Maydell wrote:
> On 23 November 2017 at 10:03, Cornelia Huck wrote:
> > On Mon, 13 Nov 2017 08:14:28 +0100
> > Thomas Huth wrote:
> >
> >> By the way, before everybody now introduces "2.12" machine types ... is
> >> there already a consensus that th
On 23/11/2017 11:57, Thomas Huth wrote:
> On 23.11.2017 11:17, Peter Maydell wrote:
>> On 23 November 2017 at 10:03, Cornelia Huck wrote:
>>> On Mon, 13 Nov 2017 08:14:28 +0100
>>> Thomas Huth wrote:
>>>
By the way, before everybody now introduces "2.12" machine types ... is
there alrea
On Wed, 22 Nov 2017, Richard Henderson wrote:
> On 11/09/2017 03:41 PM, Kirill Batuzov wrote:
> > +typedef struct TCGMemLocation {
> > +/* Offset is relative to ENV. Only fields of CPUState are accounted.
> > */
> > +tcg_target_ulong offset;
> > +tcg_target_ulong size;
> > +TCGTy
On Thu, Nov 23, 2017 at 02:41:16PM +0800, Yang Zhong wrote:
> Since there are some issues in memory alloc/free machenism
> in glibc for little chunk memory, if Qemu frequently
> alloc/free little chunk memory, the glibc doesn't alloc
> little chunk memory from free list of glibc and still
> allocat
* Peter Xu (pet...@redhat.com) wrote:
> Monitor code now can be run in more than one thread. Let the suspend
> and resume code be thread safe.
>
> Reviewed-by: Fam Zheng
> Signed-off-by: Peter Xu
> ---
> monitor.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/m
On 23.11.2017 12:11, Daniel P. Berrange wrote:
> On Thu, Nov 23, 2017 at 11:57:34AM +0100, Thomas Huth wrote:
>> On 23.11.2017 11:17, Peter Maydell wrote:
>>> On 23 November 2017 at 10:03, Cornelia Huck wrote:
On Mon, 13 Nov 2017 08:14:28 +0100
Thomas Huth wrote:
> By the way,
On 23.11.2017 12:14, Daniel P. Berrange wrote:
> On Thu, Nov 23, 2017 at 10:17:48AM +, Peter Maydell wrote:
>> On 23 November 2017 at 10:03, Cornelia Huck wrote:
>>> On Mon, 13 Nov 2017 08:14:28 +0100
>>> Thomas Huth wrote:
>>>
By the way, before everybody now introduces "2.12" machine t
On 13 November 2017 at 16:14, Mike Nawrocki
wrote:
> Signed-off-by: Mike Nawrocki
> ---
> hw/block/pflash_cfi02.c | 97
> +
> 1 file changed, 18 insertions(+), 79 deletions(-)
>
> diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
> in
On 23 November 2017 at 11:26, Peter Maydell wrote:
> On 13 November 2017 at 16:14, Mike Nawrocki
> wrote:
>> Signed-off-by: Mike Nawrocki
>> ---
>> hw/block/pflash_cfi02.c | 97
>> +
>> 1 file changed, 18 insertions(+), 79 deletions(-)
>>
>> diff
On Thu, Nov 23, 2017 at 12:24:24PM +0100, Thomas Huth wrote:
> On 23.11.2017 12:11, Daniel P. Berrange wrote:
> > On Thu, Nov 23, 2017 at 11:57:34AM +0100, Thomas Huth wrote:
> >> On 23.11.2017 11:17, Peter Maydell wrote:
> >>> On 23 November 2017 at 10:03, Cornelia Huck wrote:
> On Mon, 13 N
On 23.11.2017 11:33, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 11:25:10 +0100
> Thomas Huth wrote:
>
>> On 23.11.2017 11:08, Cornelia Huck wrote:
>>> On Thu, 23 Nov 2017 11:01:23 +0100
>>> Thomas Huth wrote:
>>>
On 23.11.2017 10:49, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 09:48
On 11/23/2017 09:20 AM, Dong Jia Shi wrote:
> * Halil Pasic [2017-11-08 17:54:20 +0100]:
>
> Hi Halil,
>
>> Add a fake device meant for testing the correctness of our css emulation.
>>
>> What we currently have is writing a Fibonacci sequence of uint32_t to the
>> device via ccw write. The wri
On 23.11.2017 12:33, Daniel P. Berrange wrote:
> On Thu, Nov 23, 2017 at 12:24:24PM +0100, Thomas Huth wrote:
>> On 23.11.2017 12:11, Daniel P. Berrange wrote:
>>> On Thu, Nov 23, 2017 at 11:57:34AM +0100, Thomas Huth wrote:
On 23.11.2017 11:17, Peter Maydell wrote:
> On 23 November 2017 a
Ping. Should I write this up as a proper proposal?
On Thu, Nov 16, 2017 at 05:20:29PM +0100, Wouter Verhelst wrote:
> On Thu, Nov 16, 2017 at 09:30:41AM -0600, Eric Blake wrote:
> > On 11/16/2017 03:51 AM, Wouter Verhelst wrote:
> >
> > >> I also remember from talking with Vladimir during KVM For
On 13 November 2017 at 16:14, Mike Nawrocki
wrote:
> Signed-off-by: Mike Nawrocki
> ---
> hw/block/pflash_cfi02.c | 143
> ++--
> 1 file changed, 102 insertions(+), 41 deletions(-)
>
> diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
> i
On 23.11.2017 12:17, Paolo Bonzini wrote:
> On 23/11/2017 11:57, Thomas Huth wrote:
[...]
>> I've put "--accel kvm:hax:tcg" also on the doable list since I don't
>> remember any objections to that idea so far -- feel free to move it to
>> the controversial list instead if you think it needs more di
On 23/11/2017 12:57, Thomas Huth wrote:
> On 23.11.2017 12:17, Paolo Bonzini wrote:
>> On 23/11/2017 11:57, Thomas Huth wrote:
> [...]
>>> I've put "--accel kvm:hax:tcg" also on the doable list since I don't
>>> remember any objections to that idea so far -- feel free to move it to
>>> the controve
在 2017/11/23 下午6:33, Cornelia Huck 写道:
On Thu, 23 Nov 2017 11:25:10 +0100
Thomas Huth wrote:
On 23.11.2017 11:08, Cornelia Huck wrote:
On Thu, 23 Nov 2017 11:01:23 +0100
Thomas Huth wrote:
On 23.11.2017 10:49, Cornelia Huck wrote:
On Thu, 23 Nov 2017 09:48:41 +0100
Thomas Huth wrote
On Thu, 23 Nov 2017 13:05:33 +0100
Paolo Bonzini wrote:
> On 23/11/2017 12:57, Thomas Huth wrote:
> > On 23.11.2017 12:17, Paolo Bonzini wrote:
> >> On 23/11/2017 11:57, Thomas Huth wrote:
> > [...]
> >>> I've put "--accel kvm:hax:tcg" also on the doable list since I don't
> >>> remember an
On 23.11.2017 13:07, Yi Min Zhao wrote:
>
>
> 在 2017/11/23 下午6:33, Cornelia Huck 写道:
>> On Thu, 23 Nov 2017 11:25:10 +0100
>> Thomas Huth wrote:
>>
>>> On 23.11.2017 11:08, Cornelia Huck wrote:
On Thu, 23 Nov 2017 11:01:23 +0100
Thomas Huth wrote:
> On 23.11.2017 10:49, Co
On 23/11/2017 13:09, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 13:05:33 +0100
> Paolo Bonzini wrote:
>
>> On 23/11/2017 12:57, Thomas Huth wrote:
>>> On 23.11.2017 12:17, Paolo Bonzini wrote:
On 23/11/2017 11:57, Thomas Huth wrote:
>>> [...]
> I've put "--accel kvm:hax:tcg" also o
On Thu, 23 Nov 2017 13:26:14 +0100
Paolo Bonzini wrote:
> On 23/11/2017 13:09, Cornelia Huck wrote:
> > On Thu, 23 Nov 2017 13:05:33 +0100
> > Paolo Bonzini wrote:
> >
> >> On 23/11/2017 12:57, Thomas Huth wrote:
> >>> On 23.11.2017 12:17, Paolo Bonzini wrote:
> On 23/11/2017 11:57
On Wed, Nov 22, 2017 at 8:09 AM, Christian Borntraeger
wrote:
> On 11/22/2017 04:23 AM, Michael Roth wrote:
>> Quoting Christian Borntraeger (2017-11-21 15:38:32)
>>> forgot to cc qemu-devel
>>>
>>> On 11/21/2017 10:37 PM, Christian Borntraeger wrote:
a quick heads up . Rc2 now triggers
>
On Thu, Nov 23, 2017 at 01:39:24PM +0100, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 13:26:14 +0100
> Paolo Bonzini wrote:
>
> > On 23/11/2017 13:09, Cornelia Huck wrote:
> > > On Thu, 23 Nov 2017 13:05:33 +0100
> > > Paolo Bonzini wrote:
> > >
> > >> On 23/11/2017 12:57, Thomas Huth wrote:
On 23/11/2017 13:39, Cornelia Huck wrote:
> I'm wondering how many people want to run e.g. x86_64-on-x86_64
> _without_ using an available kvm (and I expect those people to
> explicitly specify tcg).
I disagree. I expect them to be "power users" enough to know that
qemu-system-x86_64 defaults to
On 23/11/2017 13:59, Daniel P. Berrange wrote:
>> I'm not sure I like that. For me, qemu-kvm comes with the connotation
>> of "there used to be a fork of qemu for kvm usage, and we stuck with
>> the name because it is likely scattered through scripts".
>
> Yes, qemu-kvm is a historical artifact in
On Thu, 11/23 11:06, Christian Borntraeger wrote:
> Fam,
>
> can you disable the iotest in patchew until the block thing is solved? It
> will create a lot of unrelated
> "false positives" that make it hard to detect real issues.
Done.
Hi guys,
I'm using the hack below to do some quick kernel testing by setting
arbitrary feature bits and then make it execute the code for that
feature.
For example, boot with:
-cpu EPYC,cpuid-leaf=0x8007,ebx=0xf
to set some RAS feature bits and test newer RAS code.
Would something like tha
On Thu, 23 Nov 2017 14:02:12 +0100
Paolo Bonzini wrote:
> On 23/11/2017 13:39, Cornelia Huck wrote:
> > I'm wondering how many people want to run e.g. x86_64-on-x86_64
> > _without_ using an available kvm (and I expect those people to
> > explicitly specify tcg).
>
> I disagree. I expect them
On 16 November 2017 at 16:37, Stefan Weil wrote:
> It was broken by commit 8ecc89f6e792152496eccb684d6c8c48aba8027d which
> moved the SDL linker flags from macro libs_softmmu to macro SDL_LIBS.
>
> Signed-off-by: Stefan Weil
> ---
>
> Peter, can you apply this fix directly, or do you need a pull
On 23 November 2017 at 13:02, Paolo Bonzini wrote:
> In theory I don't like it either (and I hadn't thought about it until
> today). In practice, qemu-kvm is not going away from
> blogs/scripts/tutorials in a decade, so we might as well embrace it...
Isn't this distro-specific? In ubuntu by defa
On Thu, Nov 23, 2017 at 02:08:42PM +0100, Paolo Bonzini wrote:
> On 23/11/2017 13:59, Daniel P. Berrange wrote:
> >> I'm not sure I like that. For me, qemu-kvm comes with the connotation
> >> of "there used to be a fork of qemu for kvm usage, and we stuck with
> >> the name because it is likely sca
On 11/23/2017 12:07 PM, David Gibson wrote:
> On Fri, Nov 17, 2017 at 08:16:47AM +0100, Cédric Le Goater wrote:
>> On 11/17/2017 05:48 AM, David Gibson wrote:
>>> On Fri, Nov 10, 2017 at 03:20:09PM +, Cédric Le Goater wrote:
Currently, the ICSState 'ics' object of the sPAPR machine acts as
On 23/11/2017 14:23, Daniel P. Berrange wrote:
> On Thu, Nov 23, 2017 at 02:08:42PM +0100, Paolo Bonzini wrote:
>> On 23/11/2017 13:59, Daniel P. Berrange wrote:
I'm not sure I like that. For me, qemu-kvm comes with the connotation
of "there used to be a fork of qemu for kvm usage, and we
On 11/23/2017 12:12 PM, David Gibson wrote:
> On Fri, Nov 17, 2017 at 08:23:00AM +0100, Cédric Le Goater wrote:
>> On 11/17/2017 05:54 AM, David Gibson wrote:
>>> On Fri, Nov 10, 2017 at 03:20:14PM +, Cédric Le Goater wrote:
It will be used later on to distinguish the allocation of an LSI
On 23/11/2017 14:13, Cornelia Huck wrote:
> On Thu, 23 Nov 2017 14:02:12 +0100
> Paolo Bonzini wrote:
>
>> On 23/11/2017 13:39, Cornelia Huck wrote:
>>> I'm wondering how many people want to run e.g. x86_64-on-x86_64
>>> _without_ using an available kvm (and I expect those people to
>>> explicitl
Hello,
On a POWER9 sPAPR machine, the Client Architecture Support (CAS)
negotiation process determines whether the guest operates with an
interrupt controller using the XICS legacy model, as found on POWER8,
or in XIVE exploitation mode, the newer POWER9 interrupt model. XIVE
is a complex interrup
The sPAPR and the PowerNV core objects create the interrupt presenter
object of the CPUs in a very similar way. Let's provide a common
routine in which we use the presenter 'type' as a child identifier.
Signed-off-by: Cédric Le Goater
---
hw/intc/xics.c | 22 ++
hw/p
Each interrupt source is associated with a two bit state machine
called an Event State Buffer (ESB). The bits are named "P" (pending)
and "Q" (queued) and can be controlled by MMIO. It is used to trigger
events. See code for more details on the states and transitions.
The MMIO space for the ESB tr
The XIVE interrupt controller uses a set of tables to redirect exception
from event sources to CPU threads. The Interrupt Virtualization Entry (IVE)
table, also known as Event Assignment Structure (EAS), is one them.
The XIVE model is designed to make use of the full range of the IRQ
number space
xics_get_qirq() is only used by the sPAPR machine. Let's move it there
and change its name to reflect its scope. It will be useful for XIVE
support which will use its own set of qirqs.
Signed-off-by: Cédric Le Goater
---
hw/intc/xics.c | 12
hw/ppc/spapr.c
The 'intc' pointer of the CPU references the interrupt presenter in
the XICS interrupt mode. When the XIVE interrupt mode is available and
activated, the machine will need to reassign this pointer to reflect
the change.
Moving this assignment under the realize routine of the CPU will ease
the proc
A set of Hypervisor's call are used to configure the interrupt sources
and the event/notification queues of the guest:
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (PQ bits) entry associated with the source.
- H_INT_SET_SOURCE_CONFIG
a
These are very similar to the XICS handlers in a simpler form. They make
use of a status array for the LSI interrupts. The spapr_xive_irq() routine
in charge of triggering the CPU interrupt line will be filled later on.
Signed-off-by: Cédric Le Goater
---
hw/intc/spapr_xive.c| 55 +++
On sPAPR, the creation of the interrupt presenter depends on some of
the machine attributes. When the XIVE interrupt mode is available,
this will get more complex. So provide a machine-level helper to
isolate the process and hide the details to the sPAPR core realize
function.
Signed-off-by: Cédri
The Event Queue Descriptor (EQD) table, also known as Event Notification
Descriptor (END), is one of the internal tables the XIVE interrupt
controller uses to redirect exception from event sources to CPU
threads.
The EQD specifies on which Event Queue the event data should be posted
when an except
On 11/22/2017 05:25 PM, Cornelia Huck wrote:
> On Wed, 22 Nov 2017 15:45:56 +0100
> Boris Fiuczynski wrote:
>
>> On 11/22/2017 01:13 PM, Cornelia Huck wrote:
+object_class_property_add_bool(klass, "cssid-unrestricted",
+ prop_get_true, NUL
The IRQ numbers for the IPIs are allocated at the bottom of the IRQ
number space to preserve compatibility with XICS which only uses IRQ
numbers above 4096.
Also make sure that the allocated IRQ numbers are kept in sync between
XICS and XIVE.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c |
The XIVE interrupt sources can have different characteristics depending
on their nature and the HW level in use. The sPAPR specs provide a set of
flags to describe them :
- XIVE_SRC_H_INT_ESB the Event State Buffers are controlled with a
specific hcall H_INT_ESB and not wi
Also change the prototype to use a sPAPRMachineState and prefix them
with spapr_irq_. It will let us synchronise the IRQ allocation with
the XIVE interrupt mode when available.
Signed-off-by: Cédric Le Goater
---
hw/intc/trace-events | 4 --
hw/intc/xics_spapr.c | 114 -
It will make synchronisation easier with the XIVE interrupt mode when
available. The 'irq' parameter refers to the global IRQ number space.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/s
The XIVE interrupt presenter exposes a set of rings, also called
Thread Interrupt Management Areas (TIMA), to handle priority
management and interrupt acknowledgment among other things. There is
one ring per level of privilege, four in all. The one we are
interested in for the sPAPR machine is the
When the XIVE interrupt mode is activated, the machine needs to expose
to the guest the MMIO regions use by the controller :
- Event State Buffer (ESB)
- Thread Interrupt Management Area (TIMA)
Migration will also need to reflect the current interrupt mode in use.
Signed-off-by: Cédric Le Go
Signed-off-by: Cédric Le Goater
---
include/migration/vmstate.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 88b55df5ae0c..c0bf06e7bf89 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@
Each interrupt mode has its own specific interrupt presenter object,
that we store under the CPU object, one for XICS and one for XIVE. The
active presenter, corresponding to the current interrupt mode, is
simply selected with a lookup on the children of the CPU.
Migration and CPU hotplug also nee
Adjusting the Interrupt Pending Buffer for the O/S would allow a CPU
to process event queues of other priorities during one physical
interrupt cycle. This is not currently used by the XIVE support for
sPAPR in Linux but it is by the hypervisor.
>From Ben :
It's a way to avoid the SW replay on E
The XIVE object is designed to be always available, so it is created
unconditionally on newer machines. Depending on the configuration and
the guest capabilities, the CAS negotiation process will decide which
interrupt model to use, legacy or XIVE.
The XIVE model makes use of the full range of the
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