Adjusting the Interrupt Pending Buffer for the O/S would allow a CPU
to process event queues of other priorities during one physical
interrupt cycle. This is not currently used by the XIVE support for
sPAPR in Linux but it is by the hypervisor.
>From Ben :
It's a way to avoid the SW replay on EOI.
IE, assume you have 2 interrupts in the queue. You take the exception,
ack the first one, process it etc... Then you EOI, the HW won't send
a second notification. You need to look at the queue and continue
consuming until it's empty.
Today Linux checks the queue on EOI and use a SW mechanism to
synthesize a new pseudo-external interrupt.
This MMIO command would allow the OS to instead set back the
corresponding priority bit to 1 in the IPB and cause the HW to
re-emit the interrupt instead of SW.
Linux doesn't use this today because DD1 didn't support it for the
HV level, but other OSes might and we also might use it when we do
groups, thus allowing redistribution.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
hw/intc/spapr_xive.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index fead9c7031f3..b732aaf4f8ba 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -181,7 +181,14 @@ static bool spapr_xive_tm_is_readonly(uint8_t offset)
static void spapr_xive_tm_write_special(sPAPRXiveICP *icp, hwaddr offset,
uint64_t value, unsigned size)
{
- /* TODO: support TM_SPC_SET_OS_PENDING */
+ if (offset == TM_SPC_SET_OS_PENDING && size == 1) {
+ icp->tima_os[TM_IPB] |= priority_to_ipb(value & 0xff);
+ icp->tima_os[TM_PIPR] = ipb_to_pipr(icp->tima_os[TM_IPB]);
+ spapr_xive_icp_notify(icp);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid TIMA write @%"
+ HWADDR_PRIx" size %d\n", offset, size);
+ }
/* TODO: support TM_SPC_ACK_OS_EL */
}
--
2.13.6
