On 2016-02-17 20:09, David Kiarie wrote:
> diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
> new file mode 100644
> index 000..4264c19
> --- /dev/null
> +++ b/hw/i386/amd_iommu.h
...
> +/* extended feature support */
> +#define IOMMU_EXT_FEATURES(IOMMU_FEATURE_PREFETCH | IOMMU_FEATURE_
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 2016-02-21 09:16, Jan Kiszka wrote:
> On 2016-02-17 20:09, David Kiarie wrote:
>> diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h new file
>> mode 100644 index 000..4264c19 --- /dev/null +++
>> b/hw/i386/amd_iommu.h
>
> ...
>
>> +/* ext
On 2016-02-17 20:09, David Kiarie wrote:
> Add IVRS table for AMD IO MMU. Also reverve MMIO
> region for IO MMU via ACPI
>
> Signed-off-by: David Kiarie
> ---
> hw/i386/acpi-build.c| 98
> -
> include/hw/acpi/acpi-defs.h | 55 +
On 2016-02-17 20:09, David Kiarie wrote:
> Add IO MMU as a string to machine properties which
> is used to control whether and they type of IO MMU
> to emulate
Let's call it consistently "IOMMU", instead of "IO MMU", also in the
outputs.
Jan
signature.asc
Description: OpenPGP digital signatur
On 2016-02-17 20:09, David Kiarie wrote:
> Hello there,
>
> This is v5 of AMD IOMMU patches that fixes the issues mentioned in v4 except
> I fail to see the endian-ness issues Michael mentioned.
>
> I also stripped PIIX AMD IOMMU support since I added an MSI interrupt. One of
> the patches has
On Thu, Jan 28, 2016 at 09:23:11AM -0500, Gabriel L. Somlo wrote:
> From: Gabriel Somlo
>
> Make fw_cfg entries of type "file" available via sysfs. Entries
> are listed under /sys/firmware/qemu_fw_cfg/by_key, in folders
> named after each entry's selector key. Filename, selector value,
> and size
getrandom() has been introduced in kernel 3.17 and is now used during
the boot sequence of Debian unstable (stretch/sid).
Signed-off-by: Laurent Vivier
---
v2: fix compilation on AArch64 by conditionally define getrandom()
on TARGET_NR_getrandom AND __NR_getrandom.
linux-user/syscall.c | 13 +++
On 02/19/2016 05:30 AM, Peter Xu wrote:
One flag is added to specify whether to enable INTR for emulated
IOMMU. By default, interrupt remapping is not supportted. To enable it,
we should specify something like:
$ qemu-system-x86_64 -M q35,iommu=on,int_remap=on
Hi Peter,
Please be aware that t
On 02/19/2016 05:30 AM, Peter Xu wrote:
In ACPI DMA remapping report structure, enable INTR flag when specified.
Signed-off-by: Peter Xu
---
hw/i386/acpi-build.c | 31 ---
include/hw/i386/intel_iommu.h | 2 ++
2 files changed, 26 insertions(+), 7 deleti
On 02/19/2016 05:30 AM, Peter Xu wrote:
To enable interrupt remapping for intel IOMMU device, each IOAPIC device
in the system reported via ACPI MADT must be explicitly enumerated under
one specific remapping hardware unit. This patch adds the root-complex
IOAPIC into the default DMAR device.
Pl
On 02/21/2016 01:38 PM, Marcel Apfelbaum wrote:
On 02/19/2016 05:30 AM, Peter Xu wrote:
To enable interrupt remapping for intel IOMMU device, each IOAPIC device
in the system reported via ACPI MADT must be explicitly enumerated under
one specific remapping hardware unit. This patch adds the root
On Tuesday, February 16, 2016, Shlomo Pongratz
wrote:
>
>
> On Tuesday, February 16, 2016, Peter Maydell > wrote:
>
>> On 31 January 2016 at 15:54, Shlomo Pongratz
>> wrote:
>> > I will do a new revision of the GICv3.
>> > I needed to get a time slot from my employee in order to do the work
>>
While guest/host ABI is documented in hw/acpi/bios-linker-loader.c,
the API was left undocumented.
This adds documentation for all API functions.
Additionally, input is validated to make sure all
pointers fall within range of provided files.
To allow this validation for checksum commands,
bios_l
On Sun, Feb 21, 2016 at 10:30:26AM +0200, Michael S. Tsirkin wrote:
> On Thu, Jan 28, 2016 at 09:23:11AM -0500, Gabriel L. Somlo wrote:
> > From: Gabriel Somlo
> >
> > Make fw_cfg entries of type "file" available via sysfs. Entries
> > are listed under /sys/firmware/qemu_fw_cfg/by_key, in folders
On Sun, Feb 21, 2016 at 08:06:17AM -0500, Gabriel L. Somlo wrote:
>
> >
> > > +#if !(defined(FW_CFG_CTRL_OFF) && defined(FW_CTRL_DATA_OFF))
> > > +# if (defined(CONFIG_ARM) || defined(CONFIG_ARM64))
> > > +# define FW_CFG_CTRL_OFF 0x08
> > > +# define FW_CFG_DATA_OFF 0x00
> > > +# elif (defined
On Sun, Feb 21, 2016 at 08:06:17AM -0500, Gabriel L. Somlo wrote:
> > So for all arches which support ACPI, I think this driver
> > should just rely on ACPI.
>
> There was a discussion about that a few versions ago, and IIRC the
> conclusion was not to expect the firmware to contend for fw_cfg acc
On 2016-02-21 13:08, Marcel Apfelbaum wrote:
> On 02/21/2016 01:38 PM, Marcel Apfelbaum wrote:
>> On 02/19/2016 05:30 AM, Peter Xu wrote:
>>> To enable interrupt remapping for intel IOMMU device, each IOAPIC device
>>> in the system reported via ACPI MADT must be explicitly enumerated under
>>> one
Le 21/02/2016 04:42, Peter Crosthwaite a écrit :
On Sat, Feb 20, 2016 at 10:03 AM, Jean-Christophe DUBOIS
wrote:
Le 20/02/2016 16:30, Peter Crosthwaite a écrit :
On Sat, Feb 20, 2016 at 2:55 AM, Jean-Christophe DUBOIS
wrote:
Just to compare I tried to run Linux on QEMU emulating highbank.
F
Greetings
I am attempting to compile QEMU for Arch Liux ARM using the build files
from here:
https://projects.archlinux.org/svntogit/packages.git/tree/trunk?h=packages/qemu
I am targeting the ARMv7hf architecture. Unfortunately, I am getting an
error during the build process. I created a log
vhost currently merges regions with contiguious virtual and physical
addresses. This breaks for vhost-user since that also needs fds to
match.
Add a vhost_ops entry to compare the fds for vhost-user only.
Cc: qemu-sta...@nongnu.org
Cc: Victor Kaplansky
Signed-off-by: Michael S. Tsirkin
---
in
Hi All,
Here is my most recent successful and more complete Android Sensor
Emulation(Intel-IGD-passsthru ~ QEMU/KVM) update by me.
Watch it in action : https://www.youtube.com/watch?v=vdcOS247F-4
**== Android Sensor Emulation, fully UNLEASHED! ==**
- Fueled by GoogleNexus5
- Powered by Intel
On 21 February 2016 at 12:30, Shlomo Pongratz wrote:
> Working of re-basing the GICv3 I've noticed in the mailing list Pavel's
> patch series named "GICv3 live migration support". This patch series
> modifies GICv3 structures. I can see that this patch series was not merged
> in the latest git tha
On 21 February 2016 at 10:30, Xavier de Rauville
wrote:
> Greetings
>
> I am attempting to compile QEMU for Arch Liux ARM using the build files from
> here:
> https://projects.archlinux.org/svntogit/packages.git/tree/trunk?h=packages/qemu
>
> I am targeting the ARMv7hf architecture. Unfortunately,
On 02/21/2016 03:40 PM, Jan Kiszka wrote:
On 2016-02-21 13:08, Marcel Apfelbaum wrote:
On 02/21/2016 01:38 PM, Marcel Apfelbaum wrote:
On 02/19/2016 05:30 AM, Peter Xu wrote:
To enable interrupt remapping for intel IOMMU device, each IOAPIC device
in the system reported via ACPI MADT must be e
On 02/19/2016 05:30 AM, Peter Xu wrote:
Adding translation fault definitions for interrupt remapping. Please
refer to VT-d spec section 7.1.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu_internal.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/i386/intel_iommu_int
On 2016-02-21 16:54, Marcel Apfelbaum wrote:
> On 02/21/2016 03:40 PM, Jan Kiszka wrote:
>> On 2016-02-21 13:08, Marcel Apfelbaum wrote:
>>> On 02/21/2016 01:38 PM, Marcel Apfelbaum wrote:
On 02/19/2016 05:30 AM, Peter Xu wrote:
> To enable interrupt remapping for intel IOMMU device, each
On Sun, Feb 21, 2016 at 03:10:30PM +0200, Michael S. Tsirkin wrote:
> On Sun, Feb 21, 2016 at 08:06:17AM -0500, Gabriel L. Somlo wrote:
> >
> > >
> > > > +#if !(defined(FW_CFG_CTRL_OFF) && defined(FW_CTRL_DATA_OFF))
> > > > +# if (defined(CONFIG_ARM) || defined(CONFIG_ARM64))
> > > > +# define F
On Mon, Nov 02, 2015 at 04:49:48PM +0200, Gal Hammer wrote:
> Signed-off-by: Gal Hammer
Seems to make sense.
Acked-by: Michael S. Tsirkin
mdroth, any feedback on this one?
> ---
> qga/commands-win32.c | 66
> ++--
> 1 file changed, 64 insertio
Hello there,
Repost, AMD IOMMU patches version 6.
Changes since version 5
-Fixed macro formating issues
-changed occurences of IO MMU to IOMMU for consistency
-Fixed capability registers duplication
-Rebased to current master
David Kiarie (4):
hw/i386: Introduce AMD IOMMU
hw/core: Add AM
Add IOMMU as a string to machine properties which is
used to control whether and the type of IOMMU to emulate
Signed-off-by: David Kiarie
---
hw/core/machine.c | 28
include/hw/boards.h | 3 ++-
qemu-options.hx | 6 +++---
util/qemu-config.c | 4 ++--
4 fil
Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
depending on emulated IOMMU
Signed-off-by: David Kiarie
---
hw/i386/acpi-build.c| 208 +---
include/hw/acpi/acpi-defs.h | 55
2 files changed, 252 insertions(+), 11 deletions(-)
dif
Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU
The IOMMU does basic translation, error checking and has a
mininal IOTLB implementation
Signed-off-by: David Kiarie
---
hw/i386/Makefile.objs |1 +
hw/i386/amd_iommu.c | 1432 +
hw/i38
Add AMD IOMMU emulation support to q35 chipset
Signed-off-by: David Kiarie
---
hw/pci-host/piix.c| 1 +
hw/pci-host/q35.c | 14 --
include/hw/i386/intel_iommu.h | 1 +
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pc
On 2016-02-21 19:10, David Kiarie wrote:
> Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
> depending on emulated IOMMU
>
> Signed-off-by: David Kiarie
> ---
> hw/i386/acpi-build.c| 208
> +---
> include/hw/acpi/acpi-defs.h | 55
On Sun, Feb 21, 2016 at 9:20 PM, Jan Kiszka wrote:
> On 2016-02-21 19:10, David Kiarie wrote:
>> Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
>> depending on emulated IOMMU
>>
>> Signed-off-by: David Kiarie
>> ---
>> hw/i386/acpi-build.c| 208
>> ++
Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
depending on emulated IOMMU
Signed-off-by: David Kiarie
---
hw/i386/acpi-build.c| 98 -
include/hw/acpi/acpi-defs.h | 55 +
2 files changed, 142 insertions(+), 11 delet
On 2016-02-21 19:10, David Kiarie wrote:
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 2f0465e..dad160f 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -38,7 +38,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
> "kvm_shadow_mem=size of KVM shadow MMU\
On 2016-02-21 19:10, David Kiarie wrote:
> Hello there,
>
> Repost, AMD IOMMU patches version 6.
>
> Changes since version 5
> -Fixed macro formating issues
> -changed occurences of IO MMU to IOMMU for consistency
> -Fixed capability registers duplication
> -Rebased to current master
I suspe
Hi All
I also meet this issue.
I have two computer, one is Win7 32 another is Win7 64, Both computer meet
this issue.
My QEMU version is qemu-w32-setup-20160215
I want used EDK2 OVMF with Intel UDK Debugger tools to do source level debug
I had install com0com Virtual Com Port, and set COM3 conn
On 2016-02-17 15:05, Paolo Bonzini wrote:
>
>
> On 17/02/2016 14:53, Kevin Wolf wrote:
>> Waiting didn't fix the bug, so I tried a git bisect now and it pointed
>> me to this commit.
>>
>> I'm using HMP with the default vc backend. Starting with this commit,
>> the echo is broken sometimes, in a
On Tue, Feb 2, 2016 at 7:17 AM, Peter Maydell wrote:
> On 19 January 2016 at 07:23, Alistair Francis wrote:
>> Add the STM32F2xx ADC device. This device randomly
>> generates values on each read.
>>
>> This also includes creating a hw/adc directory.
>>
>> Signed-off-by: Alistair Francis
>
>> +st
On Tue, Feb 2, 2016 at 7:30 AM, Peter Maydell wrote:
> On 19 January 2016 at 07:23, Alistair Francis wrote:
>> Add the STM32F2xx SPI device.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> V2:
>> - Address Peter C's comments
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/ssi/Makefile.obj
On Tue, Feb 2, 2016 at 7:27 AM, Peter Maydell wrote:
> On 19 January 2016 at 07:23, Alistair Francis wrote:
>> Connect the ADC devices to the STM32F205 SoC.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> V2:
>> - Fix up the device/devices commit message
>>
>> hw/arm/stm32f205_soc.c |
Hi All,
I was trying to integrate the DRAMSim2 memory simulator [1] into QEMU.
Basically I wanted to modify the current memory interface of QEMU so that
all memory accesses will be directed to DRAMSim2. Can anyone give me
hints/comments/thoughts on how to do this? I am targeting x86-64
architectur
On 21 February 2016 at 23:35, Alistair Francis wrote:
> On Tue, Feb 2, 2016 at 7:27 AM, Peter Maydell
> wrote:
>> On 19 January 2016 at 07:23, Alistair Francis wrote:
>> You can't just wire multiple irq lines up like this; I think if
>> you do then if devices A and B both assert the IRQ and the
On Fri, Feb 19, 2016 at 08:59:44AM +0100, Greg Kurz wrote:
> On Fri, 19 Feb 2016 11:11:47 +1100
> David Gibson wrote:
>
> > On Thu, Feb 18, 2016 at 12:32:11PM +0100, Greg Kurz wrote:
> > > QEMU 2.4 broke the migration of old pseries machine with the addition
> > > of configuration sections, which
On Fri, Feb 19, 2016 at 01:33:09PM +0100, Andrea Bolognani wrote:
> I didn't say it would be hard :)
>
> I just said that such compatibility code would have to be kept
> around forever. We already support lots and lots of similar cases
> in libvirt, the difference being that in this case we would
Hello,
Thomas Huth, on Fri 19 Feb 2016 14:44:59 +0100, wrote:
> > + m->m_data -= sizeof(struct tcpiphdr) - (sizeof(struct ip)
> > ++ sizeof(struct tcphdr));
> > + m->m_len += sizeof(struct tcpiphdr) - (sizeof(struct ip)
> > +
We can know if VM in destination should go into COLO mode by refer to
the info that been migrated from PVM.
We skip this section if colo is not enabled (i.e.
migrate_set_capability colo off), so that, It not break compatibility with
migration
however the --enable-colo/disable-colo on the source/d
We add helper function colo_supported() to indicate whether
colo is supported or not, with which we use to control whether or not
showing 'x-colo' string to users, they can use qmp command
'query-migrate-capabilities' or hmp command 'info migrate_capabilities'
to learn if colo is supported.
Cc: Ju
We should not load PVM's state directly into SVM, because there maybe some
errors happen when SVM is receving data, which will break SVM.
We need to ensure receving all data before load the state into SVM. We use
an extra memory to cache these data (PVM's ram). The ram cache in secondary side
is i
configure --enable-colo/--disable-colo to switch COLO
support on/off.
COLO support is On by default.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Signed-off-by: Gonglei
Reviewed-by: Dr. David Alan Gilbert
---
v11:
- Turn COLO on in default (Eric's suggestion)
---
configure | 11
Guest will enter this state when paused to save/restore VM state
under colo checkpoint.
Cc: Eric Blake
Cc: Markus Armbruster
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Signed-off-by: Gonglei
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Eric Blake
---
qapi-schema.json | 5 ++
Switch from normal migration loadvm process into COLO checkpoint process if
COLO mode is enabled.
We add three new members to struct MigrationIncomingState,
'have_colo_incoming_thread'
and 'colo_incoming_thread' record the colo related threads for secondary VM,
'migration_incoming_co' records the
Introduce two new QEMUSizedBuffer APIs which will be used by COLO to buffer
VM state:
One is qsb_put_buffer(), which put the content of a given QEMUSizedBuffer
into QEMUFile, this is used to send buffered VM state to secondary.
Another is qsb_fill_buffer(), read 'size' bytes of data from the file i
During the time of VM's running, PVM may dirty some pages, we will transfer
PVM's dirty pages to SVM and store them into SVM's RAM cache at next checkpoint
time. So, the content of SVM's RAM cache will always be same with PVM's memory
after checkpoint.
Instead of flushing all content of PVM's RAM
This new communication path will be used for returning messages
from destination to source.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Reviewed-by: Dr. David Alan Gilbert
---
v13:
- Remove useless error report
v12:
- Add Reviewed-by tag
v11:
- Rebase master to use qemu_file_get_retu
The main process of checkpoint is to synchronize SVM with PVM.
VM's state includes ram and device state. So we will migrate PVM's
state to SVM when do checkpoint, just like migration does.
We will cache PVM's state in slave, we use QEMUSizedBuffer
to store the data, we need to know the size of VM
If users require SVM to takeover work, colo incoming thread should
exit from loop while failover BH helps backing to migration incoming
coroutine.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Reviewed-by: Dr. David Alan Gilbert
---
v12:
- Improve error message that suggested by Dave
-
We should not do failover work while the main thread is loading
VM's state, otherwise it will destroy the consistent of VM's memory and
device state.
Here we add a new failover status 'RELAUNCH' which means we should
relaunch the process of failover.
Signed-off-by: zhanghailiang
Signed-off-by: L
We need communications protocol of user-defined to control the checkpoint
process.
The new checkpoint request is started by Primary VM, and the interactive process
like below:
Checkpoint synchronizing points:
Primary Secondary
Add checkpoint-delay parameter for migrate-set-parameters, so that
we can control the checkpoint frequency when COLO is in periodic mode.
Cc: Luiz Capitulino
Cc: Eric Blake
Cc: Markus Armbruster
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Reviewed-by: Dr. David Alan Gilbert
---
v1
If VM is in COLO FT state, we should do some extra work before normal shutdown
process. SVM will ignore the shutdown command if this command is issued directly
to it, PVM will send the shutdown command to SVM if it gets this command.
Cc: Paolo Bonzini
Signed-off-by: zhanghailiang
Signed-off-by:
We leave users to choose whatever heartbeat solution they want, if the heartbeat
is lost, or other errors they detect, they can use experimental command
'x_colo_lost_heartbeat' to tell COLO to do failover, COLO will do operations
accordingly.
For example, if the command is sent to the PVM, the Pri
From: root
This is the 15th version of COLO (Still only support periodic checkpoint).
Here is only COLO frame part, you can get the whole codes from github:
https://github.com/coloft/qemu/commits/colo-v2.6-periodic-mode
There are little changes for this series except the network releated part.
Add a migrate state: MIGRATION_STATUS_COLO, enter this migration state
after the first live migration successfully finished.
We reuse migration thread, so if colo is enabled by user, migration thread will
go into the process of colo.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Signed
It is unnecessary to call qemu_savevm_state_begin() in every checkponit process.
It mainly sets up devices and does the first device state pass. These data will
not change during the later checkpoint process. So, we split it out of
colo_do_checkpoint_transaction(), in this way, we can reduce these
With this property, users can control if this filter is 'enable'
or 'disable'. The default behavior for filter is enabled.
We will skip the disabled filter when delivering packets in net layer.
Signed-off-by: zhanghailiang
Cc: Jason Wang
Cc: Yang Hongyang
---
v15:
- Rename qemu_need_skip_netfi
We record the address of the dirty pages that received,
it will help flushing pages that cached into SVM.
We record them by re-using migration dirty bitmap.
Signed-off-by: zhanghailiang
Reviewed-by: Dr. David Alan Gilbert
---
v12:
- Add Reviewed-by tag
v11:
- Split a new helper function from ori
We separate the process of saving/loading ram and device state when do
checkpoint, we add new helpers for save/load ram/device. With this change,
we can directly transfer ram from master to slave without using
QEMUSizeBufferas as assistant, which also reduce the size of extra memory
been used durin
When handling failover, we do different things according to the different stage
of failover process, here we introduce a global atomic variable to record the
status of failover.
We add four failover status to indicate the different stage of failover process.
You should use the helpers to get and s
For PVM, if there is failover request from users.
The colo thread will exit the loop while the failover BH does the
cleanup work and resumes VM.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Reviewed-by: Dr. David Alan Gilbert
---
v13:
- Add Reviewed-by tag
v12:
- Fix error report and
If the net connection between COLO's two sides is broken while colo/colo
incoming
thread is blocked in 'read'/'write' socket fd. It will not detect this error
until
connect timeout. It will be a long time.
Here we shutdown all the related socket file descriptors to wake up the blocking
operation
We may want to accept zero interval when VM FT solutions like MC
or COLO use this filter to release packets on demand.
Signed-off-by: zhanghailiang
Reviewed-by: Yang Hongyang
Cc: Jason Wang
Cc: Yang Hongyang
---
net/filter-buffer.c | 10 --
1 file changed, 10 deletions(-)
diff --git
For COLO periodic mode, it need to buffer packets that
sent by VM, and we will not release these packets until
finish a checkpoint.
Here, we add each netdev a buffer-filter that will be controlled
by COLO. It is disabled by default, and the packets will not pass
through these filters. If users don
If we start qemu with -S, the runstate will change from 'prelaunch' to 'running'
after going into colo state.
So it is necessary to update the global runstate after going into colo state.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Reviewed-by: Dr. David Alan Gilbert
---
v13:
- Add R
We can register some callback for this notifier,
this will be used by COLO to register a callback which
will add each netdev a buffer filter.
Signed-off-by: zhanghailiang
Cc: Jason Wang
Cc: Yang Hongyang
---
v14:
- New patch
---
include/net/net.h | 4
net/net.c | 33 +
If some errors happen during VM's COLO FT stage, it's important to notify the
users
of this event. Together with 'x_colo_lost_heartbeat', users can intervene in
COLO's
failover work immediately.
If users don't want to get involved in COLO's failover verdict,
it is still necessary to notify users
In COLO periodic mode, the packets from VM should not be sent
during the time interval of two checkpoints, we will release
all these buffered packets after the checkpoint process, before
VM is resumed.
In this way, we can ensure not to break the network services if
COLO goes into failover process.
For COLO's checkpoint process, we will do savevm/loadvm repeatedly.
So every time we call qemu_loadvm_section_start_full(), we will
add all sections information into loadvm_handlers list for one time.
There will be many instances in loadvm_handlers for one section,
and this will lead to memory leak
We add a new helper functions qemu_savevm_live_state(),
and make qemu_save_device_state() public.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
---
v14:
- New patch split from previous
'COLO: Separate the process of saving/loading ram and device state
---
include/sysemu/sysemu.h | 3
Do checkpoint periodically, the default interval is 200ms.
Signed-off-by: zhanghailiang
Signed-off-by: Li Zhijian
Reviewed-by: Dr. David Alan Gilbert
---
v12:
- Add Reviewed-by tag
v11:
- Fix wrong sleep time for checkpoint period. (Dave's comment)
---
migration/colo.c | 12
1 fil
Enable all buffer filters that added by COLO while
go into COLO process, and disable them while exit COLO.
Signed-off-by: zhanghailiang
Cc: Jason Wang
Cc: Yang Hongyang
---
v15:
- Re-implement colo_set_filter_status() based on COLOBufferFilters list.
- Fix the title of this patch
---
migration
There are several stages during loadvm process. In different stage,
migration incoming processes different section.
We want to control these stages more accuracy, to optimize the COLO
capability.
Here we add two new helper functions: qemu_loadvm_state_begin()
and qemu_load_device_state().
Besides,
We should not destroy the state of SVM (Secondary VM) until we receive the whole
state from the PVM (Primary VM), in case the primary fails in the middle of
sending
the state, so, here we cache the device state in Secondary before restore it.
Besides, we should call qemu_system_reset() before loa
We will use it in COLO to flush the buffered packets.
Signed-off-by: zhanghailiang
Cc: Jason Wang
Cc: Yang Hongyang
---
v14:
- New patch
---
include/net/filter.h | 2 ++
net/filter-buffer.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/net/filter.h b/include/ne
Make sure master start block replication after slave's block
replication started.
Signed-off-by: zhanghailiang
Signed-off-by: Wen Congyang
Signed-off-by: Li Zhijian
Cc: Stefan Hajnoczi
Cc: Kevin Wolf
Cc: Max Reitz
---
migration/colo.c | 48 ++
On Sat, 02/20 10:35, Gonglei wrote:
> Each RAM memory region has a unique corresponding RAMBlock.
> In the current realization, the memory region only stored
> the ram_addr which means the offset of RAM address space,
> We need to qurey the global ram.list to find the ram block
> by ram_addr if we
On 02/20/2016 03:57 AM, Dr. David Alan Gilbert wrote:
* Zhang Chen (zhangchen.f...@cn.fujitsu.com) wrote:
From: zhangchen
+static void colo_proxy_setup(NetFilterState *nf, Error **errp)
+{
+COLOProxyState *s = FILTER_COLO_PROXY(nf);
+
+if (!s->addr) {
+error_setg(errp, "filte
On 02/20/2016 03:58 AM, Dr. David Alan Gilbert wrote:
* Zhang Chen (zhangchen.f...@cn.fujitsu.com) wrote:
From: zhangchen
Add interface used by migration/colo.c
so colo framework can work with proxy
Signed-off-by: zhangchen
Signed-off-by: zhanghailiang
---
net/colo-proxy.c | 93
On 02/20/2016 10:28 PM, Max Reitz wrote:
On 19.02.2016 12:24, Alberto Garcia wrote:
On Fri 19 Feb 2016 09:26:53 AM CET, Wen Congyang wrote:
If quorum has two children(A, B). A do flush sucessfully, but B
flush failed. We MUST choice A as winner rather than just pick
anyone of them. Otherwise
* split the old SysBus init function into an instance_init
and a Device realize function
* use DeviceClass::realize instead of SysBusDeviceClass::init
Reviewed-by: Peter Maydell
Signed-off-by: xiaoqiang zhao
---
hw/timer/lm32_timer.c | 19 ---
1 file changed, 12 insertions(+),
* split the old SysBus init function into an instance_init
and a Device realize function
* use DeviceClass::realize instead of SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao
---
hw/timer/grlib_gptimer.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(
Move majority of old SysBus init's work the into instance_init.
Note:
musb_init must be called in SysBus's init, otherwise it will
break "make check" with error message as follows:
qom/object.c:1576:object_get_canonical_path_component: assertion failed:
(obj->parent != NULL)
Signed-off-by: xiao
* split the old SysBus init function into an instance_init
and a Device realize function
* use DeviceClass::realize instead of SysBusDeviceClass::init
Reviewed-by: Peter Maydell
Signed-off-by: xiaoqiang zhao
---
hw/timer/milkymist-sysctl.c | 21 +
1 file changed, 13 insert
assign puv3_ost_init to puv3_ost_info.instance_init
and drop the SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao
---
hw/timer/puv3_ost.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c
index 93650b7..72c87ba
This patch series QOM'ify timer code under hw/timer directory.
Main idea is to split the initfn's work, some to TypeInfo.instance_init
and some is placed in DeviceClass::realize.
Drop the use of SysBusDeviceClass::init if possible.
Some patches in v3:
hw/timer: QOM'ify arm_timer (pass 1)
* split the old SysBus init function into an instance_init
and a Device realize function
* use DeviceClass::realize instead of SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao
---
hw/timer/m48t59.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
rename slavio_timer_init1 to slavio_timer_init and assign
it to slavio_timer_info.instance_init, then we drop the
SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao
---
hw/timer/slavio_timer.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/timer/slavio_tim
assign etraxfs_timer_init to etraxfs_timer_info.instance_init
and drop the SysBusDeviceClass::init
Reviewed-by: Edgar E. Iglesias
Signed-off-by: xiaoqiang zhao
---
hw/timer/etraxfs_timer.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/timer/etraxfs_timer.
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