On 21 February 2016 at 23:35, Alistair Francis <alistai...@gmail.com> wrote: > On Tue, Feb 2, 2016 at 7:27 AM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> On 19 January 2016 at 07:23, Alistair Francis <alistai...@gmail.com> wrote: >> You can't just wire multiple irq lines up like this; I think if >> you do then if devices A and B both assert the IRQ and then A >> deasserts it, then the receiving device will see an IRQ deassert >> when it should not (since B still holds it high). > > I can't figure out if that is how HW actually does it. I can't find > too much in the data sheet on how these interrupts behave. > > In saying that, I am fine with what you described being the behaviour. > I don't know any better way to connect the 3 devices to one interrupt > line. Do you have any suggestions?
You're right that the data sheet is unclear, but I think the only vaguely plausible setup is that the three lines are ORed together. That way if any ADC asserts the line then the guest presumably looks at all of them to find which one has asserted it, and then writes to the register to acknowledge the interrupt. So if two ADCs assert at the same time, the guest will still (correctly) see an interrupt until it acks the second ADC. Unfortunately we don't have a qemu_irq OR gate at the moment I think, but it's a pretty simple thing to write. thanks -- PMM
