On 2016-02-17 20:09, David Kiarie wrote: > Hello there, > > This is v5 of AMD IOMMU patches that fixes the issues mentioned in v4 except > I fail to see the endian-ness issues Michael mentioned. > > I also stripped PIIX AMD IOMMU support since I added an MSI interrupt. One of > the patches has a conflict with current master but it this is mergable I > could quickly send a clean patch.
I've just made it compile over master, but something is broken, at least in the PCI capability layout: # lspci -vv -s 00:04.0 00:04.0 Generic system peripheral [0806]: Advanced Micro Devices [AMD] Device 0020 Subsystem: Red Hat, Inc Device 1100 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [64] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=0 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- <LkFail- Init- EOC- TXO- <CRCErr=0 Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Link Control 1: CFlE- CST- CFE- <LkFail- Init- EOC- TXO- <CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Revision ID: 0.00 Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00006008 Data: 0000 Capabilities: [5c] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=0 MastHost- DefDir- Link Control 0: CFlE- CST+ CFE- <LkFail- Init- EOC- TXO- <CRCErr=c Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Link Control 1: CFlE- CST- CFE+ <LkFail- Init- EOC- TXO- <CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Revision ID: 0.00 Capabilities: [58] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00005808 Data: 5c05 Capabilities: [40] <chain broken> Two times MSI, and a broken chain. At least unusual is also the reverted ordering. Please examine and fix. Thanks, Jan
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