On AST1030, reading the FMC_WDT2 register always returns 0x.
This issue is due to the aspeed_smc_read function, which checks for the
ASPEED_SMC_FEATURE_WDT_CONTROL feature. Since AST1030 was missing this
feature flag, the read operation fails and returns -1.
To resolve this, add the WDT_CO
Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set.
Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1
accesses to the PMCR register to EL2.
Smail AIDER (1):
target/arm: Code refactoring of pmreg_access/pmcr
Smail AIDER via (1):
target/arm: Trap PMCR when
Create a common helper for pmreg_access and pmreg_access_pmcr to improve
readability.
Signed-off-by: Smail AIDER
---
target/arm/cpregs-pmu.c | 40 +++-
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-
From: Smail AIDER via
Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set.
Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1
accesses to the PMCR register to EL2.
Signed-off-by: Smail AIDER
Message-Id: <20250722131925.2119169-1-smail.ai...@huawei.com>
---
On Tue, 29 Jul 2025 09:54:39 -0700
Davidlohr Bueso wrote:
> Hello,
>
> The following allows support for component basic back invalidation discovery
> and config, by exposing the BI routing table and decoder registers. Instead
> of going the type2[1] route, this series proposes adding support for
> -Original Message-
> From: Jonathan Cameron
> Sent: Thursday, July 31, 2025 11:01 AM
> To: Manos Pitsidianakis
> Cc: qemu-devel@nongnu.org; Peter Maydell ;
> qemu-...@nongnu.org; Gustavo Romero ;
> Shameerali Kolothum Thodi
> Subject: Re: [PATCH] hw/arm: add static NVDIMMs in device
On Wed, 30 Jul 2025 17:52:45 -0300
Fabiano Rosas wrote:
> Don't use the 'max' cpu for migration testing of aarch64. That cpu
> does not provide a stable set of features and is expected to break
> migration from time to time.
Whilst I can see the motivation, doesn't this leave us with a lack of
c
On Wed, 30 Jul 2025 15:21:41 +0300
Manos Pitsidianakis wrote:
> NVDIMM is used for fast rootfs with EROFS, for example by kata
> containers. To allow booting with static NVDIMM memory, add them to the
> device tree in arm virt machine.
>
> This allows users to boot directly with nvdimm memory de
Hi Cédric, Michael
> From: Cédric Le Goater
> Sent: Tuesday, July 29, 2025 5:12 PM
> To: Jamin Lin ; Michael Tokarev
> ; Peter Maydell ; Steven Lee
> ; Troy Lee ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Hao Wu ;
> Havard Skinne
Changes:
7b1eb5f ast27x0: Fix Makefile to unconditionally set CC to support correct
cross-compilation
601d410 ast27x0: Fix missing SCU module reset for SSP and TSP initialization
80768e4 ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory
from DTB
f8ab635 ast27x0: Show build dat
On Fri, Jul 25, 2025 at 02:53:37PM +0100, Jonathan Cameron wrote:
> On Fri, 18 Jul 2025 21:35:45 +0800
> peng guo wrote:
>
> > When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> > 9p device fails to initialize properly. The kernel reports the following:
> >
> > vi
On Sat, 26 Jul 2025 20:50:35 +0800
peng guo wrote:
> On Fri, Jul 25, 2025 at 02:53:37PM +0100, Jonathan Cameron wrote:
> > On Fri, 18 Jul 2025 21:35:45 +0800
> > peng guo wrote:
> >
> > > When using a CXL Type 3 device together with a virtio 9p device in QEMU,
> > > the
> > > 9p device fails
Hi Michael, Cédric
> From: Michael Tokarev
> Sent: Monday, July 28, 2025 3:12 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Steven Lee
> ; Troy Lee ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Hao Wu ;
> Havard Skinnem
ao Wu ;
> Havard Skinnemoen
> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
> SCU initialization support
>
> On 7/27/25 21:51, Michael Tokarev wrote:
> > On 17.07.2025 06:40, Jamin Lin via wrote:
> >> The updated boot ROM includes logic
On Fri, Jul 25, 2025 at 02:53:37PM +0100, Jonathan Cameron wrote:
> On Fri, 18 Jul 2025 21:35:45 +0800
> peng guo wrote:
>
> > When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> > 9p device fails to initialize properly. The kernel reports the following:
> >
> > vi
On Tue, 17 Jun 2025 12:06:49 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> Define a new CXL host bridge type (TYPE_CXL_HOST). This is an
> independent CXL host bridge which combined GPEX features (ECAM, MMIO
> windows and irq) and CXL Host Bridge Component Registers (CHBCR).
>
> The root bus
On Tue, 17 Jun 2025 12:06:48 +0800
wangyuquan wrote:
> This renames some descriptions and definitions of pxb cxl host
> bridge, since the original names can be confusing.
>
> Signed-off-by: Yuquan Wang
Fair enough.
Reviewed-by: Jonathan Cameron
> ---
> hw/pci-bridge/pci_expander_bridge.c | 8
On Tue, 17 Jun 2025 12:19:46 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> This creates a specific CXL host bridge (0001:00) with two cxl
> root ports on sbsa-ref. And the memory layout provides separate
> space windows for the cxl host bridge in the sbsa-ref memmap:
>
> - 64K CXL Host Brid
On Thu, 10 Jul 2025 20:13:38 +0530
Arpit Kumar wrote:
> -added assert-deassert PERST implementation
> for physical ports (both USP and DSP's).
> -assert PERST involves bg operation for holding 100ms.
> -reset PPB implementation for physical ports.
>
> Signed-off-by: Arpit Kumar
Hi Arpit,
Mino
On Thu, 10 Jul 2025 20:13:37 +0530
Arpit Kumar wrote:
> -Storing physical ports info during enumeration.
> -Refactored changes using physical ports info for
> Identify Switch Device (Opcode 5100h) & Get Physical Port State
> (Opcode 5101h) physical switch FM-API command set.
>
> Signed-off-by:
On Fri, 18 Jul 2025 21:35:45 +0800
peng guo wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> 9p device fails to initialize properly. The kernel reports the following:
>
> virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1
> 9p
On Mon, 21 Jul 2025 18:22:28 +0100
wrote:
> From: Shiju Jose
>
> Memory sparing is defined as a repair function that replaces a portion of
> memory with a portion of functional memory at that same DPA. The
> subclasses for this operation vary in terms of the scope of the sparing
> being perform
On Mon, 21 Jul 2025 18:22:27 +0100
wrote:
> From: Davidlohr Bueso
I tweaked the title to mention Post Package Repair. If anyone is ever
looking for that particular maintenance command they might want to know
it is in here from the title.
>
> This adds initial support for the Maintenance comm
On Mon, 21 Jul 2025 18:22:22 +0100
wrote:
> From: Shiju Jose
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in
On Thu, 24 Jul 2025 03:43:56 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Jul 18, 2025 at 09:35:45PM +0800, peng guo wrote:
> > When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> > 9p device fails to initialize properly. The kernel reports the following:
> >
> > vi
Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set.
Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1
accesses to the PMCR register to EL2.
Signed-off-by: Smail AIDER
---
target/arm/cpregs-pmu.c | 24 ++--
1 file changed, 22 insertions(+), 2 de
thing like this from virtio_error():
VQ 0 size 0x100 Guest index 0x0 inconsistent with Host index 0xc: delta 0xfff4
This patch suppresses this consistency check if we're loading the
initial VMStateDescriptions via iterative migration and unsuppresses
it for the stop-and-copy phase when
From: Shiju Jose
Add updates for the CXL spec rev3.2 changes, in the CXL events reporting
and QMP command to inject CXL events.
Add maintenance support and emulation support for memory Post Package
Repair(PPR) and memory sparing control features.
Add support for reporting the memory sparing eve
From: Shiju Jose
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature() to the local scope where they are used.
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
hw/cxl/cxl-mailbox-utils.c | 17 +++--
1 file changed, 7 insertions(+), 10
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command t
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in
From: Shiju Jose
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The
subclasses for this operation vary in terms of the scope of the sparing
being performed. The Cacheline sparing subclass refers to a sparing
a
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error C
From: Davidlohr Bueso
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the reque
From: Shiju Jose
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands
On Fri, 18 Jul 2025 19:20:45 +0300
Vadim Chichikalyuk wrote:
> Previous patch changed the SPCR ACPI table for AArch64 virt:
> @@ -15,2 +15,2 @@
> -[008h 0008 001h]Revision : 02
> -[009h 0009 001h]Checksum : B1
> +[008h 0008 001h]Revision
On Fri, 18 Jul 2025 19:20:42 +0300
Vadim Chichikalyuk wrote:
> The UART clock frequency field of the SPCR table was added in revision 3.
> Currently, build_spcr() treats revision 3 tables the same as revision 2 and
> only includes this field in revision 4 tables.
Given this isn't in the ACPI spe
On Fri, 18 Jul 2025 19:20:44 +0300
Vadim Chichikalyuk wrote:
> On the ARM virt machine, there is currently no way to programmatically
> discover the frequency of the UART reference clock solely through the use of
> UEFI/ACPI (without the DTB). The SPCR table can include this information
> as of r
On Fri, 18 Jul 2025 19:20:43 +0300
Vadim Chichikalyuk wrote:
> Signed-off-by: Vadim Chichikalyuk
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-di
When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
9p device fails to initialize properly. The kernel reports the following:
virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1
9pnet_virtio virtio0: probe with driver 9pnet_virtio failed with
> -Original Message-
> From: Nicolin Chen
> Sent: Friday, July 18, 2025 9:12 AM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; imamm...@redh
> -Original Message-
> From: Nicolin Chen
> Sent: Friday, July 18, 2025 5:14 AM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; imamm...@redh
after launch. For example, when the PSP is launched first
to enable SSP via SCU, the test framework cannot dynamically attach to the SSP
console afterward to verify its behavior.
Due to this limitation, the test case for AST2700FC has been modified to use
vBootROM (`ast27x0_bootrom.bin`) instead of
In the previous design, both the PSP and TSP were started together during
SoC initialization. However, on real hardware, the TSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the TSP firmware binary into shared memory via DRAM remap, and then
The updated boot ROM includes logic to initialize and enable SSP/TSP using SCU
registers, based on reserved-memory regions defined in the device tree.
Its source code is available at:
https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c2102fa98e
Build Information:
Build Date
This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x224):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via
This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.
Two MemoryRegion
mory between the main CPU (PSP) and the
+ * coprocessors. Coprocessors access this shared SRAM region through a
+ * MemoryRegion alias mapped to a different physical address.
+ *
+ * Similarly, the SCU is a single hardware block shared across all
+ * processors. Coprocessors ac
``-device loader``:
+
+In this approach, users manually load firmware and assign entry points via
QEMU loader devices.
+By default, the PSP begins execution at address ``0x43000``, the load
address of the bl31
+firmware. The SSP and TSP start in the powered-off state and must be
explicitly
AST2700 has a 128KB SRAM, physically mapped at 0x1000–0x1001 for the
main CA35 processor. The TSP coprocessor accesses this same memory at a
different memory address: 0x7000–0x7001.
To support this shared memory model, this commit introduces "tsp.sram_mr_alias",
a "MemoryRegion" al
AST2700 has a 128KB SRAM, physically mapped at 0x1000–0x1001 for the
main CA35 processor. The SSP coprocessor accesses this same memory at a
different memory address: 0x7000–0x7001.
To support this shared memory model, this commit introduces "ssp.sram_mr_alias",
a "MemoryRegion" al
This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42e00 (32MB) to TSP SDRAM offset 0x0
This region corresponds to the d
window.
One MemoryRegion alias is attached to the SCU via QOM property link:
- tsp-sdram-remap: maps PSP DRAM at 0x42E00 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base
(alias
at a specific offset. This alias is
mapped into the coprocessor's SDRAM address space, allowing both PSP and the
coprocessor (SSP/TSP) to access the same physical memory through their
respective
views — PSP via its DRAM, and the coprocessor via its SDRAM.
The remapping is configured throug
U register defaults.
+ * Therefore, DRAM must be fully initialized before coprocessors can
+ * attach aliases to it.
*
- * Similarly, the SCU is a single hardware block shared across all
- * processors. Coprocessors access it via a MemoryRegion alias that maps
- * t
AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000–0x12C03FFF
from the perspective of the main CA35 processor (PSP). The TSP coprocessor
accesses
this same SCU block at a different address: 0x72C02000–0x72C03FFF.
To support this shared SCU model, this commit introduces "tsp.scu_
In the previous design, both the PSP and SSP were started together during
SoC initialization. However, on real hardware, the SSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the SSP firmware binary into shared memory via DRAM remap, and then
This patch implements SSP reset and power control logic in the SCU for AST2700.
It introduces support for the following behavior:
1. SSP Reset Trigger (via SCU 0x220):
- SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL_1.
2. SSP Reset State and Source Hold (via SCU 0x120
According to the AST2700 design, the TSP coprocessor uses its own SDRAM
instead of SRAM. Additionally, all three coprocessors—SSP, TSP, and PSP—share
a common SRAM block. In the previous implementation, the TSP memory region
was labeled and sized as "SRAM", but in practice it was being used as TSP'
Introduces support for loading a vbootrom image into the dedicated vbootrom
memory region in the AST2700 Full Core machine.
Additionally, it implements a mechanism to extract the content of fmc_cs0
flash data(backend file) and copy it into the memory-mapped region
corresponding to ASPEED_DEV_SPI_B
In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was initialized
and realized at the machine level (e.g., AST2700FC). However, to make sure the
coprocessors can work together properly—such as using the same SRAM, sharing
the SCU, and having consistent memory remapping—we need to chan
According to the AST2700 design, the SSP coprocessor uses its own SDRAM
instead of SRAM. Additionally, all three coprocessors—SSP, TSP, and PSP—share
a common SRAM block. In the previous implementation, the SSP memory region
was labeled and sized as "SRAM", but in practice it was being used as SSP'
In the previous design, the TSP coprocessor (aspeed27x0tsp-soc) was initialized
and realized at the machine level (e.g., AST2700FC). To allow proper
integration between coprocessors—such as shared use of SRAM, SCU, and memory
remap configuration—this commit moves TSP initialization into the AST2700
coprocessor reset via SCU registers.
Jamin Lin (21):
hw/arm/aspeed_ast27x0-fc: Support VBootRom
hw/arm/ast27x0: Move SSP coprocessor initialization from machine to
SoC leve
hw/arm/ast27x0: Move TSP coprocessor initialization from machine to
SoC leve
hw/arm/aspeed_ast27x0-ssp: Switch SSP
On Tue, Jul 15, 2025 at 08:19:04AM +0200, Cédric Le Goater wrote:
> commit ad8e0e8a0088 removed the "==" underlining the file title
> which broke documentation rendering. Add it back.
>
> Fixes: ad8e0e8a0088 ("docs: add support for gb200-bmc")
> Cc: Ed Tanous
> Reported-by: Peter Maydell
> S
> -Original Message-
> From: Nicolin Chen
> Sent: Wednesday, July 16, 2025 3:58 AM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; nath...@nvi
On Wed, Jul 16, 2025 at 05:23:57PM +0800, Yi Liu wrote:
> On 2025/7/16 12:05, Konstantin Belousov wrote:
> > On Wed, Jul 16, 2025 at 12:01:44PM +0800, Yi Liu wrote:
> > > On 2025/7/15 20:27, CLEMENT MATHIEU--DRIF wrote:
> > > >
> > > >
> > > > On 15/07/2025 10:27 am, David Woodhouse wrote:
> > >
On Tue, 15 Jul 2025 10:01:21 -0700
Nicolin Chen wrote:
> On Tue, Jul 15, 2025 at 11:29:41AM +0100, Jonathan Cameron wrote:
> > > +if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,
> > > + IOMMU_VIOMMU_TYPE_ARM_SMMUV3,
> > > +
backend is allowed with
> >> >arm-smmuv3,accel=on",
> >> >+ pdev->name);
> >> >+exit(1);
> >>
> >> Seems aggressive for a hotplug, could we fail hotplug instead of kill
> QEMU?
> >
> >Hotpl
> -Original Message-
> From: Duan, Zhenzhong
> Sent: Wednesday, July 16, 2025 4:39 AM
> To: Nicolin Chen
> Cc: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; eric.au...@redhat.com;
> peter.mayd...@linaro.org; j...@nvidia.com; ddut...@redhat.com;
> berra...@
accel) {
> > +return;
> > + }
> > +
> > +g_hash_table_foreach(bs->configs, smmuv3_accel_ste_range, range);
>
> This will not work correctly?
>
> The bs->configs is a cache that gets an entry inserted to when a
> config is fetched via sm
But things like IORT mappings aren't able
> to get refreshed since the OS is likely already booted.
Why do we need IORT mappings to be refreshed during hotplug?
AFAICS, the mappings are created per host bridge Ids. And how is this
different from a host machine doing hotplug?
Even an
>
> -Original Message-
> From: Nicolin Chen
> Sent: Tuesday, July 15, 2025 6:23 PM
> To: Jonathan Cameron
> Cc: Shameerali Kolothum Thodi
> ; Linuxarm
> ; qemu-...@nongnu.org; qemu-
> de...@nongnu.org; eric.au...@redhat.com; peter.mayd...@linaro.org;
> j...@nvidia.com; ddut...@redhat.com
> -Original Message-
> From: Duan, Zhenzhong
> Sent: Tuesday, July 15, 2025 11:46 AM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> nicol...@nvidia.com; ddut...@redhat.com; berra..
On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SI
On Mon, 14 Jul 2025 16:59:41 +0100
Shameer Kolothum wrote:
> Now user can set "accel=on". Have fun!
>
> Signed-off-by: Shameer Kolothum
Hard to argue with this one ;)
Reviewed-by: Jonathan Cameron
> ---
> hw/arm/smmu-common.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm
On Mon, 14 Jul 2025 16:59:40 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SIDSIZE
On Mon, 14 Jul 2025 16:59:39 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Use the provided smmuv3-accel helper functions to issue the
> invalidation commands to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-internal.h | 11 +++
On Mon, 14 Jul 2025 16:59:38 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Helpers will batch the commands and issue at once to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-accel.c| 65 +
On Mon, 14 Jul 2025 16:59:34 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -If found an existing viommu reuse that.
>(Devices behind the same physical SMMU should share an S2 HWPT)
> -Else,
> Allocate a viommu with the nested parent S2
the IOMMU address space
>
> Note: On ARM, MSI doorbell addresses are also translated via SMMUv3.
> Hence, if a vfio-pci device is behind the SMMuv3 with translation enabled,
> it must return the IOMMU address space for MSI. Support for this will be
> added in a follow-up patc
On Mon, 14 Jul 2025 16:59:31 +0100
Shameer Kolothum wrote:
> Also setup specific PCIIOMMUOps for accel SMMUv3 as accel
> SMMUv3 will have different handling for those ops callbacks
> in subsequent patches.
>
> The "accel" property is not yet added, so users cannot set it at this
> point. It will
On Mon, 14 Jul 2025 16:59:30 +0100
Shameer Kolothum wrote:
> Allows to retrieve the PCIIOMMUOps based on the SMMU type. This will be
> useful when we add support for accelerated SMMUV3 in subsequent patches
> as that requires a different set of callbacks for iommu ops.
>
> No special handling is
On Mon, 14 Jul 2025 16:59:29 +0100
Shameer Kolothum wrote:
> Subsequent patches for smmuv3 accel support will make use of this.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
Various trivial things inline. In general looks fine.
J
> ---
> hw/ar
On Mon, 14 Jul 2025 16:59:28 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate an iommufd device's virtual device (in the user
> space) per a viommu instance.
Same trivial suggestion as in patch 1. Also feel free to ignore.
On Mon, 14 Jul 2025 16:59:27 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate a viommu object.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
One trivial comment inline. Feel free to ignore.
> ---
> backends/iomm
On Mon, Jul 14, 2025 at 05:41:22PM +0100, David Woodhouse wrote:
> On 14 July 2025 15:28:09 GMT+01:00, Yi Liu wrote:
> >Hi David,
> >
> >On 2025/7/14 16:00, David Woodhouse wrote:
> >> From: David Woodhouse
> >>
> >> FreeBSD does both, and this appears to be perfectly valid. The VT-d
> >> spec e
On Mon, Jul 14, 2025 at 09:14:17AM -0700, Nicolin Chen wrote:
> Hi Shameer,
>
> Thank you for sending the v3.
>
> On Mon, Jul 14, 2025 at 04:59:26PM +0100, Shameer Kolothum wrote:
> > Branch for testing:
> [...]
> > Tested on a HiSilicon platform with multiple SMMUv3s.
> >
> > ./qemu-system-aarc
On Mon, Jul 14, 2025 at 01:04:02PM -0700, Nicolin Chen wrote:
> On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> > From: Nicolin Chen
> >
> > Not all fields in the SMMU IDR registers are meaningful for userspace.
> > Only the following fields can be used:
> >
> > - IDR0: ST_
On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SI
On Mon, 14 Jul 2025 10:04:44 +0200
Eric Auger wrote:
> This series enables ACPI PCI hotplug/hotunplug on ARM.
> It is not enabled by default and ACPI PCI hotplug can
> be selected by setting:
>
> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>
> Expected benefits should be similar t
On 7/14/25 5:12 PM, Ilya Maximets wrote:
On 7/11/25 11:44 AM, Daniel Borkmann wrote:
Extend 'inhibit=on' setting with the option to specify a pinned XSK map
path along with a starting index (default 0) to push the created XSK
sockets into. Example usage:
# ./build/qemu-system-x86_64 [...] \
From: Anisa Su
Prepatory patch for following FMAPI Add/Release Patches. Refactors part
of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
function to create DC Event Records and insert in the event log.
Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
accessed b
From: Anisa Su
Add a lock on the bitmap of each CXLDCRegion in preparation for the next
patch which implements FMAPI Set DC Region Configuration. This command
can modify the block size, which means the region's bitmap must be updated
accordingly.
The lock becomes necessary when commands that add
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 88 ++
1 file changed, 88 insertions(+)
diff --git
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 of set to merge:
- Fixed blksize check in set dc region config
- Added check that it is a power of 2 (and host-ut
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 ++
hw/cxl/cxl-mailbox-utils.c | 109
hw/mem
From: Anisa Su
FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4
Very similar to previously implemented command 0x4801.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 for merge:
- Added a missing : in a comment similar to Fan
From: Anisa Su
FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 106 +
1 file changed, 106 insertions(+)
diff --gi
From: Anisa Su
Move definition/enum to cxl_events.h for shared use in next patch
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_events.h | 15 +++
hw/mem/cxl_type3.c | 15 ---
2 files changed, 15 insertions(
1 - 100 of 2762 matches
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