This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address
remapping
through SCU registers. It only supports setting the PSP DRAM base and size,
which
are then aliased into the TSP-visible SDRAM window.
One MemoryRegion alias is attached to the SCU via QOM property link:
- tsp-sdram-remap: maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base
(alias offset)
and mapping size.
|------------------------------------------|
|----------------------------|
| PSP DRAM | | TSP SDRAM
|
|------------------------------------------|
|----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000
|
| remap base |------> | - fixed target addr
|
| size: 32MB (SCU_194) | |
|
|------------------------------------------|
|----------------------------|
SCU VMState version remains at 3, as it was already bumped in a previous commit.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_ast27x0.c | 3 +++
hw/misc/aspeed_scu.c | 24 +++++++++++++++++++++++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 408f821379..5e7c80feb1 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -42,6 +42,7 @@ struct AspeedSCUState {
MemoryRegion *ssp_sdram_remap1;
MemoryRegion *ssp_sdram_remap2;
+ MemoryRegion *tsp_sdram_remap;
};
#define AST2400_A0_SILICON_REV 0x02000303U
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 587c042c30..23096bda34 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -839,6 +839,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev,
Error **errp)
object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap2",
OBJECT(&a->ssp.sdram_remap2_alias),
&error_abort);
+ object_property_set_link(OBJECT(&s->scu), "tsp-sdram-remap",
+ OBJECT(&a->tsp.sdram_remap_alias),
+ &error_abort);
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index df379cafbe..21a0d1ad5c 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -143,13 +143,15 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
-/* SSP */
+/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c)
#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
+#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -630,6 +632,8 @@ static const Property aspeed_scu_properties[] = {
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_LINK("ssp-sdram-remap2", AspeedSCUState, ssp_sdram_remap2,
TYPE_MEMORY_REGION, MemoryRegion *),
+ DEFINE_PROP_LINK("tsp-sdram-remap", AspeedSCUState, tsp_sdram_remap,
+ TYPE_MEMORY_REGION, MemoryRegion *),
};
static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
@@ -956,6 +960,22 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr
offset,
data &= 0x3fffffff;
memory_region_set_size(mr, data);
break;
+ case AST2700_SCU_TSP_CTRL_1:
+ if (s->tsp_sdram_remap == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ /* remapped to SOC DRAM by adding data << 4 */
+ memory_region_set_alias_offset(s->tsp_sdram_remap,
+ (uint64_t) data << 4);
+ break;
+ case AST2700_SCU_TSP_REMAP_SIZE_2:
+ if (s->tsp_sdram_remap == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(s->tsp_sdram_remap, data);
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -989,6 +1009,8 @@ static const uint32_t
ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
+ [AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
+ [AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
--
2.43.0
