This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x224):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via SCU 0x160):
- Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an
external source.
- Bit 1 (RST) is a software-controlled bit used to request holding TSP in
reset.
- If an external reset source is present and bit 1 is set, bit 9
(RST_HOLD_RB)
will also be asserted to indicate the TSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset is
deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to
TSP_CTRL_0 to release
the hold and power on TSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after
execution.
4. Reset Status Clear (via SCU 0x224):
- The reset status can be cleared by writing 1 to bit 9 (RW1C) of
SYS_RST_CLR_2,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold
is active.
5. TSP Power Control Logic:
- handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and invokes
arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).
- handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, also
asserts
RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).
The default values are based on EVB (evaluation board) register dump
observations.
TSP reset control shares the same helper functions and register bit layout as
SSP,
with logic selected by cpuid and distinct external reset sources.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 50f3f6ff17..ee31a9aabd 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -152,6 +152,7 @@
#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c)
#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
+#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SSP_TSP_ENABLE BIT(0)
@@ -162,6 +163,9 @@
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
+#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)
+#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)
+#define AST2700_SCU_SYS_RST_TSP BIT(9)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -923,7 +927,7 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque,
hwaddr offset,
static void handle_ssp_tsp_on(struct AspeedSCUState *s, int cpuid)
{
- int reg = AST2700_SCU_SSP_CTRL_0;
+ int reg = (cpuid == 4) ? AST2700_SCU_SSP_CTRL_0 : AST2700_SCU_TSP_CTRL_0;
uint32_t val = s->regs[reg];
val &= ~AST2700_SSP_TSP_RST_SRC_RB;
@@ -937,7 +941,7 @@ static void handle_ssp_tsp_on(struct AspeedSCUState *s, int
cpuid)
static void handle_ssp_tsp_off(struct AspeedSCUState *s, int cpuid)
{
- int reg = AST2700_SCU_SSP_CTRL_0;
+ int reg = (cpuid == 4) ? AST2700_SCU_SSP_CTRL_0 : AST2700_SCU_TSP_CTRL_0;
uint32_t val = s->regs[reg];
val |= AST2700_SSP_TSP_RST_RB;
@@ -973,7 +977,8 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr
offset,
switch (reg) {
case AST2700_SCU_SSP_CTRL_0:
- cpuid = 4;
+ case AST2700_SCU_TSP_CTRL_0:
+ cpuid = (reg == AST2700_SCU_SSP_CTRL_0) ? 4 : 5;
oldval = s->regs[reg];
data &= 0xff;
active = oldval ^ data;
@@ -1068,6 +1073,24 @@ static void aspeed_ast2700_scu_write(void *opaque,
hwaddr offset,
}
s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
return;
+ case AST2700_SCU_SYS_RST_CTRL_2:
+ data &= 0x00001fff;
+ oldval = s->regs[reg];
+ active = data & ~oldval;
+ if (data & AST2700_SCU_SYS_RST_TSP) {
+ handle_ssp_tsp_off(s, 5);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_2:
+ data &= 0x00001fff;
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_2];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_TSP) {
+ handle_ssp_tsp_on(s, 5);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_2] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1102,9 +1125,11 @@ static const uint32_t
ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
+ [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
[AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
+ [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
--
2.43.0
