AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000–0x12C03FFF
from the perspective of the main CA35 processor (PSP). The SSP coprocessor
accesses
this same SCU block at a different address: 0x72C02000–0x72C03FFF.
To support this shared SCU model, this commit introduces "ssp.scu_mr_alias",
a "MemoryRegion" alias of the original SCU region ("s->scu.iomem"). The alias is
realized during SSP SoC setup and mapped into the SSP's SoC memory map.
Additionally, because the SCU must be realized before the SSP can create an
alias
to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
This ensures that PSP and SSP access a consistent SCU state, as expected by
hardware.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-ssp.c | 9 ++-------
hw/arm/aspeed_ast27x0.c | 24 ++++++++++++++++++------
3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 1e4f8580b1..65a452123b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -135,6 +135,7 @@ struct Aspeed27x0SSPSoCState {
UnimplementedDeviceState scuio;
MemoryRegion memory;
MemoryRegion sram_mr_alias;
+ MemoryRegion scu_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index b7b886f4bf..0a58b8ea4b 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -135,9 +135,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
- object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
@@ -198,10 +196,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState
*dev_soc, Error **errp)
&a->sram_mr_alias);
/* SCU */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
+ &a->scu_mr_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@@ -273,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass
*klass, const void *dat
dc->realize = aspeed_soc_ast27x0ssp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->spis_num = 0;
sc->ehcis_num = 0;
sc->wdts_num = 0;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 8272a28ad5..04b8b340ba 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -641,6 +641,10 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState
*dev, Error **errp)
mr = &s->sram;
memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s),
"ssp.sram.alias",
mr, 0, memory_region_size(mr));
+
+ mr = &s->scu.iomem;
+ memory_region_init_alias(&a->ssp.scu_mr_alias, OBJECT(s), "ssp.scu.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
return false;
}
@@ -788,14 +792,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev,
Error **errp)
sc->memmap[ASPEED_DEV_SCUIO]);
/*
- * Coprocessors must be realized after the SRAM region.
+ * Coprocessors must be realized after the SRAM and SCU regions.
+ *
+ * The SRAM is used as shared memory between the main CPU (PSP) and the
+ * coprocessors. Coprocessors access this shared SRAM region through a
+ * MemoryRegion alias mapped to a different physical address.
+ *
+ * Similarly, the SCU is a single hardware block shared across all
+ * processors. Coprocessors access it via a MemoryRegion alias that maps
+ * to a different address than the one used by the main CPU.
*
- * The SRAM is used for shared memory between the main CPU (PSP) and
- * coprocessors. The coprocessors accesses this shared SRAM region
- * through a memory alias mapped to a different physical address.
+ * Therefore, both the SRAM and SCU must be fully initialized before the
+ * coprocessors can create aliases pointing to them.
*
- * Therefore, the SRAM must be fully initialized before the coprocessors
- * can create aliases pointing to it.
+ * To ensure correctness, the device realization order is explicitly
+ * managed:
+ * coprocessors are initialized only after SRAM and SCU are ready.
*/
if (mc->default_cpus > sc->num_cpus) {
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
--
2.43.0
