On Tue, Jan 21, 2025 at 02:38:44PM +0100, Paolo Bonzini wrote:
> Queued with the tweaks suggested by Zoltan and Zhao; thanks!
Thank you Paolo :-)
On Tue, Jan 21, 2025 at 09:31:25PM +0800, Zhao Liu wrote:
> On Tue, Jan 21, 2025 at 10:06:50AM +0800, Tao Su wrote:
> > Date: Tue, 21 Jan 2025 10:06:50 +0800
> > From: Tao Su
> > Subject: [PATCH 4/4] docs: Add GNR, SRF and CWF CPU models
> > X-Mailer: git-send-e
On Tue, Jan 21, 2025 at 09:34:58AM -0800, Pawan Gupta wrote:
> On Tue, Jan 21, 2025 at 10:06:47AM +0800, Tao Su wrote:
> > Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
> > of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl,
> > bhi-
On Tue, Jan 21, 2025 at 04:12:48AM +0100, BALATON Zoltan wrote:
> On Tue, 21 Jan 2025, Tao Su wrote:
> > Update GraniteRapids, SierraForest and ClearwaterForest CPU models in
> > section "Preferred CPU models for Intel x86 hosts".
> >
> > Also introd
mitigated in stepping 3.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1b9c11022c..6db8d6c9ba 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4549,6
]
- DDPD_U CPUID.(EAX=7,ECX=2):EDX[bit 3]
- BHI_NO IA32_ARCH_CAPABILITIES[bit 20]
Add above and all features of SierraForest-v2 CPU model to new CPU model
ClearwaterForest.
[1] https://cdrdv2.intel.com/v1/dl/getContent/671368
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c
Update GraniteRapids, SierraForest and ClearwaterForest CPU models in
section "Preferred CPU models for Intel x86 hosts".
Also introduce bhi-no, gds-no and rfds-no in doc.
Suggested-by: Zhao Liu
Signed-off-by: Tao Su
---
docs/system/cpu-models-x86.rs
is required to prevent BHI.
Make BHI_NO bit available to guests.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6db8d6c9ba..33fb27a611 100644
--- a/target/i386
model ClearwaterForest based on
SierraForest-v2 CPU model.
Tao Su (4):
target/i386: Introduce SierraForest-v2 model
target/i386: Export BHI_NO bit to guests
target/i386: Add new CPU model ClearwaterForest
docs: Add GNR, SRF and CWF CPU models
docs/system/cpu-models-x86.rst.inc | 42
t
tead of checking for
> have_filtered_features.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: commit bccfb846fd52 ("target/i386: add AVX10 feature and AVX10 version
> property")
> Signed-off-by: Zhao Liu
Reviewed-by: Tao Su
> ---
> v5: new commit.
> ---
> target
4825.870939-1-tao1...@linux.intel.com/
> for reference.
>
> Signed-off-by: Paolo Bonzini
The patch name is still for avx-vnni-int16.
LGTM,
Reviewed-by: Tao Su
On Fri, Nov 01, 2024 at 12:52:12AM +0800, Zhao Liu wrote:
> > @@ -7578,7 +7607,27 @@ static bool x86_cpu_filter_features(X86CPU *cpu,
> > bool verbose)
> > }
> > }
> >
> > -return x86_cpu_have_filtered_features(cpu);
> > +have_filtered_features = x86_cpu_have_filtered_featu
On Fri, Nov 01, 2024 at 10:44:23AM +0800, Zhao Liu wrote:
> > > prefix is just used to print warning. So here we should check prefix
> > > for warn_report.
> > >
> > > +} else if (env->avx10_version) {
> > > +if (prefix) {
> > > +warn_report("%s: avx10.%d.", prefix, env->av
From: Paolo Bonzini
Right now, QEMU is using the "feature" and "bits" fields of ExtSaveArea
to query the accelerator for the support status of extended save areas.
This is a problem for AVX10, which attaches two feature bits (AVX512F
and AVX10) to the same extended save states.
To keep the AVX10
From: Paolo Bonzini
Prepare for filtering non-boolean features such as AVX10 version.
Signed-off-by: Paolo Bonzini
Reviewed-by: Zhao Liu
Signed-off-by: Tao Su
---
target/i386/cpu.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b
Update GraniteRapids CPU model to add AVX10 and the missing features(ss,
tsc-adjust, cldemote, movdiri, movdir64b).
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/20241028024512.156724-7-tao1...@linux.intel.com
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
7_1_EDX_AVX10 and
CPUID_24_0_EBX will be disabled automatically.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/20241028024512.156724-5-tao1...@linux.intel.com
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 16
targe
From: Paolo Bonzini
Signed-off-by: Paolo Bonzini
Reviewed-by: Zhao Liu
---
target/i386/cpu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1ff1af032e..b912dba2e5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1
urn bool from x86_cpu_filter_features
Tao Su (5):
target/i386: add AVX10 feature and AVX10 version property
target/i386: add CPUID.24 features for AVX10
target/i386: Add feature dependencies for AVX10
target/i386: Add AVX512 state when AVX10 is supported
target/i386: Introduce GraniteRa
Introduce features for the supported vector bit lengths.
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1...@linux.intel.com
Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1...@linux.intel.com
Signed-off-by: Paolo Bonzini
Reviewed-by: Zhao Liu
10 version can never be 0, the default
value of avx10-version is set to 0 to determine whether it is specified by
user. The default can come from the device model or, for the max model,
from KVM's reported value.
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/2024102802451
Su
Signed-off-by: Paolo Bonzini
Reviewed-by: Zhao Liu
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d8d86edd67..cc7e4ce665 100644
--- a/target/i386
On Thu, Oct 31, 2024 at 03:18:37PM +0800, Zhao Liu wrote:
> > > > > > > @@ -7674,13 +7682,21 @@ static bool
> > > > > > > x86_cpu_filter_features(X86CPU *cpu, bool verbose)
> > > > > > > &eax_0, &ebx_0, &ecx_0,
> > > > > > > &edx_0);
> > > > > > > uin
On Thu, Oct 31, 2024 at 01:52:24PM +0800, Xiaoyao Li wrote:
[ ... ]
> > I mainly want to let avx10_version be assigned only when -cpu host or max,
> > so that it can be distinguished from the cpu model. This should also be
> > Paolo's original intention in v2.
>
> avx10_version needs to be assig
On Wed, Oct 30, 2024 at 11:55:34PM +0800, Zhao Liu wrote:
> On Wed, Oct 30, 2024 at 10:05:51PM +0800, Tao Su wrote:
> > Date: Wed, 30 Oct 2024 22:05:51 +0800
> > From: Tao Su
> > Subject: Re: [PATCH 4/8] target/i386: add AVX10 feature and AVX10 version
> > property
&g
On Wed, Oct 30, 2024 at 09:21:36PM +0800, Zhao Liu wrote:
> > > > Introduce avx10-version property so that avx10 version can be controlled
> > > > by user and cpu model. Per spec, avx10 version can never be 0, the
> > > > default
> > > > value of avx10-version is set to 0 to determine whether it i
property
> > X-Mailer: git-send-email 2.47.0
> >
> > From: Tao Su
> >
> > When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10
> > Converged Vector ISA leaf" containing fields for the version number and
> > the supported vector b
On Wed, Oct 30, 2024 at 09:35:43AM +0100, Paolo Bonzini wrote:
> Il mer 30 ott 2024, 04:23 Tao Su ha scritto:
>
> > > I don't have a Granite Rapids machine, so please test! :)
> >
> > I test it on Granite Rapids and all meet expection with my minor changes on
&g
:)
I test it on Granite Rapids and all meet expection with my minor changes on
patch4 :)
>
> Paolo
>
> Paolo Bonzini (3):
> target/i386: cpu: set correct supported XCR0 features for TCG
> target/i386: do not rely on ExtSaveArea for accelerator-supported XCR0 bits
> t
On Tue, Oct 29, 2024 at 04:18:54PM +0100, Paolo Bonzini wrote:
> From: Tao Su
[ ... ]
> static void max_x86_cpu_realize(DeviceState *dev, Error **errp)
> {
> Object *obj = OBJECT(dev);
> +X86CPU *cpu = X86_CPU(dev);
> +CPUX86State *env = &c
On Tue, Oct 29, 2024 at 10:58:39PM +0800, Zhao Liu wrote:
> On Mon, Oct 28, 2024 at 10:45:12AM +0800, Tao Su wrote:
> > Date: Mon, 28 Oct 2024 10:45:12 +0800
> > From: Tao Su
> > Subject: [PATCH 6/6] target/i386: Introduce GraniteRapids-v2 model
> > X-Mailer: git-send-e
On Tue, Oct 29, 2024 at 10:47:04PM +0800, Zhao Liu wrote:
> Hi Tao,
>
> On Mon, Oct 28, 2024 at 10:45:10AM +0800, Tao Su wrote:
> > Date: Mon, 28 Oct 2024 10:45:10 +0800
> > From: Tao Su
> > Subject: [PATCH 4/6] target/i386: Add feature dependencies for AVX10
> >
On Tue, Oct 29, 2024 at 09:25:53AM +0100, Paolo Bonzini wrote:
> On 10/28/24 03:45, Tao Su wrote:
> > @@ -6835,6 +6850,26 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
> > uint32_t count,
> > }
> > break;
> > }
> >
On Tue, Oct 29, 2024 at 09:49:39AM +0100, Paolo Bonzini wrote:
> On 10/28/24 10:25, Tao Su wrote:
> > On Mon, Oct 28, 2024 at 09:41:14AM +0100, Paolo Bonzini wrote:
> > > On 10/28/24 03:45, Tao Su wrote:
> > > > AVX10 state enumeration in CPUID leaf D and enablin
On Mon, Oct 28, 2024 at 11:10:45PM +0800, Xiaoyao Li wrote:
> On 10/28/2024 10:45 AM, Tao Su wrote:
> > Introduce avx10-version property so that avx10 version can be controlled
> > by user and cpu model. Per spec, avx10 version can never be 0, the default
> > value of avx10-v
On Mon, Oct 28, 2024 at 11:04:07PM +0800, Xiaoyao Li wrote:
> On 10/28/2024 10:45 AM, Tao Su wrote:
> > +case 0x24: {
> > +*eax = 0;
> > +*ebx = 0;
> > +*ecx = 0;
> > +*edx = 0;
> > +if (!(env->fe
On Mon, Oct 28, 2024 at 11:45:25AM +0100, Paolo Bonzini wrote:
> On 10/28/24 11:02, Tao Su wrote:
> > On Mon, Oct 28, 2024 at 09:45:39AM +0100, Paolo Bonzini wrote:
> > > On 10/28/24 03:45, Tao Su wrote:
> > > > Since the highest supported vector length for a proc
On Mon, Oct 28, 2024 at 09:45:39AM +0100, Paolo Bonzini wrote:
> On 10/28/24 03:45, Tao Su wrote:
> > Since the highest supported vector length for a processor implies that
> > all lesser vector lengths are also supported, add the dependencies of
> > the supported vector l
On Mon, Oct 28, 2024 at 09:41:14AM +0100, Paolo Bonzini wrote:
> On 10/28/24 03:45, Tao Su wrote:
> > AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register
> > are identical to AVX512 state regardless of the supported vector lengths.
> >
> > Given tha
When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10
Converged Vector ISA leaf" containing fields for the version number and
the supported vector bit lengths.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.
Update GraniteRapids CPU model to add AVX10 and the missing features(ss,
tsc-adjust, cldemote, movdiri, movdir64b).
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
Introduce avx10-version property so that avx10 version can be controlled
by user and cpu model. Per spec, avx10 version can never be 0, the default
value of avx10-version is set to 0 to determine whether it is specified by
user.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386
/784267
---
Tao Su (6):
target/i386: Add AVX512 state when AVX10 is supported
target/i386: add avx10-version property
target/i386: Add CPUID.24 leaf for AVX10
target/i386: Add feature dependencies for AVX10
target/i386: Add support for AVX10 in CPUID enumeration
target/i386: Introduce
7_1_EDX_AVX10 and
CPUID_24_0_EBX will be disabled automatically.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c | 16
target/i386/cpu.h | 4
2 files changed, 20 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 91fae0dcb7..9666db
enable bit, AVX10 will be enabled
automatically when using '-cpu host' and KVM advertises AVX10 to
userspace.
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Signed-off-by: Tao Su
---
target/i386/cpu.c | 14 ++
target/i386/cpu.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1ff1af032e..d845ff5e4e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7177,6 +7177,13 @@ static void
xpose monitor_puts to rest of code)
Reviwed-by: Xiaoyao Li
Reviewed-by: Markus Armbruster
Signed-off-by: Tao Su
---
v1 -> v2:
- Instead revert the broken part of commit bf0c50d4aa85
- Add Markus's Reviewed-by
v1:
- https://lore.kernel.org/all/20240320052118.520378-1-tao1...@li
On Wed, Mar 20, 2024 at 08:17:36AM +0100, Philippe Mathieu-Daudé wrote:
> Hi Tao,
>
> On 20/3/24 07:02, Markus Armbruster wrote:
> > Tao Su writes:
> >
> > > monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
> > > may have a pa
On Wed, Mar 20, 2024 at 07:02:46AM +0100, Markus Armbruster wrote:
> Tao Su writes:
>
> > monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
> > may have a parameter with NULL monitor pointer. Check the monitor pointer
> > before calling
monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
may have a parameter with NULL monitor pointer. Check the monitor pointer
before calling monitor_puts().
Fixes: bf0c50d4aa85 (monitor: expose monitor_puts to rest of code)
Reviwed-by: Xiaoyao Li
Signed-off-by: T
doesn’t support TSX and RTM but supports TAA_NO. When RTM is
not enabled in host, KVM will not report TAA_NO. So, just don't include
TAA_NO in SierraForest CPU model.
[1] https://cdrdv2.intel.com/v1/dl/getContent/671368
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Signed-off-by: Tao Su
-
On Wed, Mar 13, 2024 at 02:27:18PM +0100, Gerd Hoffmann wrote:
> Query kvm for supported guest physical address bits, in cpuid
> function 8008, eax[23:16]. Usually this is identical to host
> physical address bits. With NPT or EPT being used this might be
> restricted to 48 (max 4-level pagin
On Fri, Mar 08, 2024 at 05:36:52PM +0100, Igor Mammedov wrote:
> On Wed, 6 Dec 2023 21:19:23 +0800
> Tao Su wrote:
>
> > SierraForest is Intel's first generation E-core based Xeon server
> > processor, which will be released in the first half of 2024.
> >
On Tue, Mar 05, 2024 at 11:52:33AM +0100, Gerd Hoffmann wrote:
> Query kvm for supported guest physical address bits, in cpuid
> function 8008, eax[23:16]. Usually this is identical to host
> physical address bits. With NPT or EPT being used this might be
> restricted to 48 (max 4-level pagin
On Mon, Mar 04, 2024 at 09:54:40AM +0800, Xiaoyao Li wrote:
> On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
> > query kvm for supported guest physical address bits using
> > KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
> > (leaf 0x8008, eax, bits 16-23).
> >
> > Signed-off-by: Ger
On Wed, Jan 31, 2024 at 01:34:31PM +0100, Igor Mammedov wrote:
> On Tue, 30 Jan 2024 21:34:36 +0800
> Tao Su wrote:
>
> > On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> > > On Thu, 6 Jul 2023 13:49:49 +0800
> > > Tao Su wrote:
> > &
On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> On Thu, 6 Jul 2023 13:49:49 +0800
> Tao Su wrote:
>
> > The GraniteRapids CPU model mainly adds the following new features
> > based on SapphireRapids:
> > - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
Kindly ping for any comments.
Thanks,
Tao
model.
Currently LAM and LASS are not enabled in KVM mainline yet, will add
them after merged.
Signed-off-by: Tao Su
---
The new features can be found in Intel ISE[1].
LAM has just been accepted by KVM[2].
Although we would like to include all SierraForest features in the first
version of the C
On Wed, Aug 30, 2023 at 12:41:11PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
Thanks Paolo!
CPUID
definition for AMX-COMPLEX, AMX-COMPLEX will be enabled automatically when
using '-cpu host' and KVM advertises AMX-COMPLEX to userspace.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
KVM part of advertising AMX-COMPLEX CPUID bit already has been applied to
kvm-x86 misc.
On Fri, Jul 07, 2023 at 12:52:37PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
Paolo, thanks!
>
> Paolo
>
https://lore.kernel.org/all/63d85cc76d4cdc51e6c732478b81d8f13be11e5a.1687551881.git.pawan.kumar.gu...@linux.intel.com/
Lei Wang (1):
target/i386: Add few security fix bits in ARCH_CAPABILITIES into
SapphireRapids CPU model
Tao Su (5):
target/i386: Add FEAT_7_1_EDX to adjust feature level
target/i386
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions.
Signed-off-by: Tao Su
Reviewed-by: Igor Mammedov
---
target/i386/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386
]
- SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
- FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
Signed-off-by: Tao Su
Tested-by: Xuelian Guo
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 136
feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 26 ++
target/i386/cpu.h | 4
2 files changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
07H.
Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
enumeration")
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5688cabb4..952744af97 100644
-
From: Lei Wang
SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
enabled, which are related to some security fixes.
Add version 2 of SapphireRapids CPU model with those bits enabled also.
Signed-off-by: Lei Wang
Signed-off-by: Tao Su
---
target/i386/cpu.c | 13
On Tue, Jun 27, 2023 at 01:55:23PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:11 +0800
> Tao Su wrote:
>
> > The GraniteRapids CPU model mainly adds the following new features based
> > on SapphireRapids:
> >
> > - PREFETCHITI CPUID.(EAX=7,ECX=1)
On Mon, Jun 26, 2023 at 03:03:12PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:07 +0800
> Tao Su wrote:
>
> > MCDT_NO bit indicates HW contains the security fix and doesn't need to
> > be mitigated to avoid data-dependent behaviour for certain instructions.
On Mon, Jun 26, 2023 at 02:39:15PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:05 +0800
> Tao Su wrote:
>
> > Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> > non-zero,
> Can you clarify when/why that happens?
When start a VM on Granit
On Fri, Jun 16, 2023 at 12:01:52PM +0800, Wang, Lei wrote:
> On 6/16/2023 11:23, Tao Su wrote:
> > This patch series mainly updates SapphireRapids CPU model and adds
> > new CPU model EmeraldRapids and GraniteRapids.
> >
> > Bit 13 (ARCH_CAP_FBSDP_NO), bit 14 (AR
ts in ARCH_CAPABILITIES into
SapphireRapids CPU model
Qian Wen (1):
target/i386: Add new CPU model EmeraldRapids
Tao Su (5):
target/i386: Add FEAT_7_1_EDX to adjust feature level
target/i386: Add support for MCDT_NO in CPUID enumeration
target/i386: Allow MCDT_NO if host supports
target/i386
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions
and feature names.
Signed-off-by: Tao Su
---
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git
MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
Signed-off-by: Tao Su
Tested-by: Xuelian Guo
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 136 ++
1 file changed, 136 insertions
From: Lei Wang
Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
fixes.
Add version 2 of SapphireRapids CPU model with those bits enabled also.
Signed-off-by: Lei Wang
Signed-off-by: Tao Su
---
target/i386
alone cpu model.
Signed-off-by: Qian Wen
Reviewed-by: Xiaoyao Li
Signed-off-by: Tao Su
---
Changes to original patch
(https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian@intel.com/)
- Add MSR_ARCH_CAP_SBDR_SSDP_NO, MSR_ARCH_CAP_FBSDP_NO and
MSR_ARCH_CAP_PSDP_NO
---
target/i
Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
non-zero, guest may report wrong maximum number sub-leaves in leaf
07H. So add FEAT_7_1_EDX to adjust feature level.
Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
enumeration")
Signed-off-
feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 26 ++
target/i386/cpu.h | 4
2 files changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
On Wed, Apr 26, 2023 at 02:24:18PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
>
> Paolo
>
Paolo, thanks!
Tao
Intel platforms Granite Rapids/Sierra Forest introduce below new
instructions and CPUID leaves:
- CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
- AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
- AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
- AVX-NE-CONVERT CPUI
without
loss of accuracy or added SW overhead.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 21]
Add CPUID definition for AMX-FP16.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a
compatibility.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 5]
Add CPUID definition for AVX-NE-CONVERT.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386
):EAX[bit 7]
Add CPUID definition for CMPCCXADD.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4bad3d41d3..e54e13d050 100644
--- a
-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eee1e5c25f..719e6a2636 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -894,7 +894,7
the
destination dword element size operand.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 4]
AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word
FEAT_7_1_EDX for this leaf.
Add CPUID definition for AVX-VNNI-INT8.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target
-IFMA.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ed08a52619..9aaa373e97 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
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