Add AVX10.1 CPUID support, i.e. add AVX10 support bit via CPUID.(EAX=07H, ECX=01H):EDX[bit 19] and new CPUID leaf 0x24H so that guest OS and applications can query the AVX10 CPUIDs directly. The AVX10.1 spec can be found in [1], it is worth mentioning that VL128 (CPUID.(EAX=24H, ECX=00H):EBX[bit 16]) was dropped in rev3.0, but it will be added back and reserved as 1 (SDM and AVX10.2 spec[2] have already described).
Since GraniteRapids (stepping 1) is the first platform to support AVX10, introduce GraniteRapids-v2 CPU model to add AVX10 in this patch set, and add some missing features as well. [1] https://cdrdv2.intel.com/v1/dl/getContent/671200 [2] https://cdrdv2.intel.com/v1/dl/getContent/828965 --- Changelog: v2->v3: - Move assigning avx10_version from max_x86_cpu_realize() to x86_cpu_expand_features(). - Add CPUIDs of vector lengths back in cpu_x86_cpuid(). - Update comment on x86_cpu_expand_features(). (Zhao) - Tell user about revised version if version is invalid. (Zhao) - Handle when AVX10 enable bit is disabled but user sets avx10-verion. (Zhao) - Add Zhao's Reviewed-by and Xuelian's Tested-by. v2: https://lore.kernel.org/all/20241029151858.550269-1-pbonz...@redhat.com/ v1: https://lore.kernel.org/all/20241028024512.156724-1-tao1...@linux.intel.com/ --- Paolo Bonzini (3): target/i386: cpu: set correct supported XCR0 features for TCG target/i386: do not rely on ExtSaveArea for accelerator-supported XCR0 bits target/i386: return bool from x86_cpu_filter_features Tao Su (5): target/i386: add AVX10 feature and AVX10 version property target/i386: add CPUID.24 features for AVX10 target/i386: Add feature dependencies for AVX10 target/i386: Add AVX512 state when AVX10 is supported target/i386: Introduce GraniteRapids-v2 model target/i386/cpu.c | 177 ++++++++++++++++++++++++++++++++++---- target/i386/cpu.h | 16 ++++ target/i386/kvm/kvm-cpu.c | 4 - target/i386/kvm/kvm.c | 3 +- 4 files changed, 176 insertions(+), 24 deletions(-) base-commit: 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29 -- 2.34.1
