On Mon, Oct 28, 2024 at 09:45:39AM +0100, Paolo Bonzini wrote: > On 10/28/24 03:45, Tao Su wrote: > > Since the highest supported vector length for a processor implies that > > all lesser vector lengths are also supported, add the dependencies of > > the supported vector lengths. If all vector lengths aren't supported, > > clear AVX10 enable bit as well. > > > > Note that the order of AVX10 related dependencies should be kept as: > > CPUID_24_0_EBX_AVX10_128 -> CPUID_24_0_EBX_AVX10_256, > > CPUID_24_0_EBX_AVX10_256 -> CPUID_24_0_EBX_AVX10_512, > > CPUID_24_0_EBX_AVX10_VL_MASK -> CPUID_7_1_EDX_AVX10, > > I think you need to add a set of dependencies so that avx10 cannot be set, > unless all the older AVX features that it's composed of are available. From > the manual these are > > AVX512F, AVX512CD, AVX512VW, AVX512DQ, AVX512_VBMI, AVX512_IFMA, > AVX512_VNNI, AVX512_BF16, AVX512_VPOPCNTDQ, AVX512_VBMI2, VAES, GFNI, > VPCLMULQDQ, AVX512_BITALG, AVX512_FP16.
Thanks for such a quick review!! AVX10.1 spec said: Intel AVX-512 will continue to be supported on P-core-only processors for the foreseeable future to support legacy applications. However, new vector ISA features will only be added to the Intel AVX10 ISA moving forward. While Intel AVX10/512 includes all Intel AVX-512 instructions, it important to note that applications compiled to Intel AVX-512 with vector length limited to 256 bits are not guaranteed to be compatible on an Intel AVX10/256 processor. I.e. AVX10/256 processors will support old AVX-512 instructions (limited to 256 bits and enumerated by AVX10) but not set AVX-512 related CPUIDs. So, I think we can't add these dependencies…
