Re: [PATCH v9] target/riscv: Add Smdbltrp ISA extension enable switch

On Thu, Jan 16, 2025 at 11:17 PM Clément Léger wrote: > > Add the switch to enable the Smdbltrp ISA extension and disable it for > the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double > trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid > taking a double trap.

[PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-2-e83d79

[PULL 05/50] target/riscv: add shvstvala

We already have sstvala, and our vstval follows the same rules as stval, so we can claim to support shvstvala too. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-5-dbarb...@ventanamicro.com> Signed-off-by: Alist

[PULL 23/50] target/riscv: Add Smrnmi mnret instruction

Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-5-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/insn32.decode

[PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-3-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.

[PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-4-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- include/hw/riscv/riscv_ha

[PULL 34/50] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by

[PULL 36/50] target/riscv: Invoke pmu init after feature enable

From: Atish Patra The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID

[PULL 11/50] target/riscv: use RISCVException enum in exception helpers

to RISCVException in generate_exception() to guarantee that all callers of riscv_raise_exception() will use the enum. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250106173734.412353-2-dbarb...@ventanamicro.com> Signe

[PULL 16/50] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250106102346.1100149-5-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target

[PULL 44/50] target/riscv: Add Smdbltrp CSRs handling

From: Clément Léger Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-7-cle...@rivosinc.com> Signed-off-by: Al

[PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions

From: Atish Patra This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message

[PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250116223609.81594-1-phi...@linaro.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 15 +++ hw/char/trace-events | 4 2 files changed, 7 inse

[PULL 13/50] target/riscv: Remove obsolete pointer masking extension code.

uro Acked-by: Alistair Francis Message-ID: <20250106102346.1100149-2-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 33 +--- target/riscv/cpu_bits.h | 87 -- target/riscv/cpu.c | 13 +- target/riscv/cpu_helper.c| 5

[PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-7-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/internals.h

[PULL 31/50] target/riscv: Support generic CSR indirect access

. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-4-e83d797ae...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h

qemu-devel@nongnu.org

]; ... } s; Directly use that instead of the &first_cpu global. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250112231344.34632-3-phi...@linaro.org> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+),

[PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

From: Atish Patra Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-11-e83d797ae...@rivosinc.com> Signed-off-by: Al

[PULL 46/50] target/riscv: Implement Smdbltrp behavior

From: Clément Léger When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-9-

[PULL 24/50] target/riscv: Add Smrnmi cpu extension

x27;s disable Smrnmi for the 'max' type CPU for now. We can re-enable it once OpenSBI includes proper support for it. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Signed-off-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Fran

[PULL 30/50] target/riscv: Enable S*stateen bits for AIA

corresponding checks in the CSR accessor functions. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-3-e83d797ae...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 85 +- 1 file c

[PULL 42/50] target/riscv: Implement Ssdbltrp exception handling

From: Clément Léger When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-5-cle...@rivosinc.com

[PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-6-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 22 -- target

[PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-2-frank.ch...@sifive.com> Signed-off-by:

[PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-8-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target

[PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250

[PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi

MNPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-7-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 +

[PULL 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch

From: Clément Léger Add the switch to enable the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-6-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+)

[PULL 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior

: Alistair Francis Message-ID: <20250110125441.3208676-4-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 35 ++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c

[PULL 08/50] target/riscv: add shvsatpa

From: Daniel Henrique Barboza shvsatpa is defined in RVA22 as: "All translation modes supported in satp must be supported in vsatp." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Fran

[PULL 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache

with the same PSCID, but only the former one should be invalidated. Signed-off-by: Jason Chien Reviewed-by: Daniel Henrique Barboza Message-ID: <20241108110147.11178-1-jason.ch...@sifive.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c

[PULL 37/50] target/riscv: Add implied rule for counter delegation extensions

extension is enabled. Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-10-e83d797ae...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 12 +++- 1 file changed, 11 insertions

[PULL 39/50] target/riscv: Fix henvcfg potentially containing stale bits

ing henvcfg upper part when writing it with write_henvcfgh(). Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-2-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 10 -

[PULL 02/50] target/riscv: rvv: speed up small unit-stride loads and stores

: Craig Blackmore Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Message-ID: <20241218142353.1027938-3-craig.blackm...@embecosm.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 16 1 file changed, 16 insertions(+) diff --git a/

[PULL 40/50] target/riscv: Add Ssdbltrp CSRs handling

From: Clément Léger Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message

[PULL 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0

: <20250113194410.1307494-1-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu.c | 23 +++ 2 files changed, 25 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index aef896ba00..b410

[PULL 33/50] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-6-e83d797ae...@rivosinc.com>

[PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch

From: Clément Léger Add the switch to enable the Smdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-10-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 inse

[PULL 35/50] target/riscv: Add counter delegation/configuration support

Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-8-e83d797ae...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 304 +++-- 1 file changed, 292 inse

[PULL 09/50] target/riscv: add shgatpa

ue for TCG. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-9-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 382 -> 390 bytes 2 files c

[PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior

From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-8-

[PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu

u-Daudé Reviewed-by: Alistair Francis Message-ID: <20250112231344.34632-2-phi...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm_riscv.h | 4 +++- hw/riscv/virt.c | 2 +- target/riscv/kvm/kvm-cpu.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletio

[PULL 00/50] riscv-to-apply queue

The following changes since commit 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5: Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu into staging (2025-01-16 09:03:43 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to

[PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-4-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 5 +++ target/riscv/cpu_helper.

[PULL 21/50] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-3-frank.ch...@sifive.com> Sign

[PULL 10/50] target/riscv/tcg: add sha

ys present) - Shgatpa (always present) We can claim support for 'sha' by checking if we have RVH and ssstateen. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-10-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis -

[PULL 12/50] target/riscv: add trace in riscv_raise_exception()

.) riscv_exception 2 (illegal_instruction) on epc 0x1053a Illegal instruction (core dumped) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106173734.412353-3-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c

[PULL 07/50] target/riscv: add shvstvecd

for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-7-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 364 -> 374 bytes 2 fi

[PULL 04/50] target/riscv: add shcounterenw

ed-by: Alistair Francis Message-ID: <20241218114026.1652352-4-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 332 -> 346 bytes 2 files changed, 1 insertion(+) diff --git a/target/riscv/cp

[PULL 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names

From: Craig Blackmore Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Reviewed-by: Richard Henderson Message-ID: <20241218142353.1027938-2-craig.blackm...@embecosm.com> Signed-off-by: Alistair F

[PULL 06/50] target/riscv: add shtvala

Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-6-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 356 -> 364 bytes 2 files changed, 1 insertion(+) diff --git a/target/r

[PULL 03/50] riscv/gdbstub: add V bit to priv reg

ff-by: Yanfeng Liu Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- target/riscv/gdbstub.c | 23 +++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index c07df972f1..18e88f416a 100644

Re: [PATCH] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

On Fri, Jan 17, 2025 at 8:37 AM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/char/riscv_htif.c | 15 +++ > hw/char/trace-events | 4 > 2 files changed, 7 insertions(+), 12 deletions(-) > >

Re: [PATCH] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

On Fri, Jan 17, 2025 at 8:37 AM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/char/riscv_htif.c | 15 +++ > hw/char/trace-events | 4 > 2 files changed, 7 insertions(+), 12 del

Re: [RFC 1/4] spdm-socket: add seperate send/recv functions

On Wed, Jan 8, 2025 at 12:04 AM Wilfred Mallawa via wrote: > > This is to support uni-directional transports such as SPDM > over Storage. As specified by the DMTF DSP0286. > > Signed-off-by: Wilfred Mallawa > --- > backends/spdm-socket.c | 25 + > include/system/spd

Re: [PATCH v2] target/riscv: Support Supm and Sspm as part of Zjpm v1.0

On Tue, Jan 14, 2025 at 5:45 AM wrote: > > From: Alexey Baturo > > Rebased against alistair/riscv-to-apply.next > > [v1]: I removed the lines above, as we don't want to include the changelog or rebase notes in the commit message > The Zjpm v1.0 spec states there should be Supm and Sspm extensio

Re: [PATCH v8 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions

On Fri, Jan 10, 2025 at 10:55 PM Clément Léger wrote: > > A double trap typically arises during a sensitive phase in trap handling > operations — when an exception or interrupt occurs while the trap > handler (the component responsible for managing these events) is in a > non-reentrant state. This

Re: [PATCH] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache

On Fri, Nov 8, 2024 at 9:03 PM Jason Chien wrote: > > This commit introduces a translation tag to avoid invalidating an entry > that should not be invalidated when IOMMU executes invalidation commands. > E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping > of single stage transla

Re: [PATCH v5 00/11] Add RISC-V Counter delegation ISA extension support

On Fri, Jan 10, 2025 at 6:23 PM Atish Patra wrote: > > This series adds the counter delegation extension support. The counter > delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA > extensions. > > 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional >

qemu-devel@nongnu.org

On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé wrote: > > Pass RISCVCPU to kvm_riscv_get_timebase_frequency(), > then access the first vCPU via Virt::Array::Hart[] > rather than the &first_cpu global, which is going to > be removed as part of the heterogeneous emulation > effort. > > Phili

qemu-devel@nongnu.org

t; RISCVCPU *harts; > ... > > } soc[VIRT_SOCKETS_MAX]; > ... > > } s; > > Directly use that instead of the &first_cpu global. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c

Re: [PATCH 1/2] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu

declares > the RISCVCPU typedef. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm_riscv.h | 4 +++- > hw/riscv/virt.c | 2 +- > target/riscv/kvm/kvm-cpu.c | 4 ++-- > 3 files changed, 6 inserti

Re: [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable

iable > behaving like before when used for wiring IRQ lines. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/arm/stellaris.c | 21 +++-- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/hw/arm

Re: [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init()

y: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/arm/b-l475e-iot01a.c| 2 +- > hw/arm/microbit.c | 2 +- > hw/arm/mps2-tz.c | 2 +- > hw/arm/mps2.c | 2 +- > hw/arm/msf2-som.c | 2 +- > hw/arm/musca.c

Re: [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'

ilippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > include/hw/arm/nrf51_soc.h | 2 +- > hw/arm/nrf51_soc.c | 18 +- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nr

Re: [PATCH v7 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions

On Tue, Dec 17, 2024 at 7:10 PM Clément Léger wrote: > > A double trap typically arises during a sensitive phase in trap handling > operations — when an exception or interrupt occurs while the trap > handler (the component responsible for managing these events) is in a > non-reentrant state. This

Re: [PATCH v4 00/11] Add RISC-V Counter delegation ISA extension support

On Wed, Dec 4, 2024 at 9:18 AM Atish Patra wrote: > > This series adds the counter delegation extension support. The counter > delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA > extensions. > > 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional >

Re: [PATCH v4 08/11] target/riscv: Add counter delegation/configuration support

scountovf virtualization. > > Signed-off-by: Kaiwen Xue > Co-developed-by: Atish Patra > Signed-off-by: Atish Patra Acked-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 304 > ++--- > 1 file changed, 292

Re: [PATCH v4 10/11] target/riscv: Add implied rule for counter delegation extensions

plied rule so that these extensions are enabled by default > if the sscfg extension is enabled. > > Reviewed-by: Daniel Henrique Barboza > Signed-off-by: Atish Patra Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 12 +++- > 1 file changed, 11 insertions(+)

Re: [PATCH v4 05/11] target/riscv: Add properties for counter delegation ISA extensions

Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 963f1f3af9ae..82edd28e2e1d 100644

Re: [PATCH v4 04/11] target/riscv: Support generic CSR indirect access

ng them depends on > whether each extension is enabled and the value stored in xiselect. > > Co-developed-by: Atish Patra > Signed-off-by: Atish Patra > Signed-off-by: Kaiwen Xue Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu_bits.h | 28

Re: [PATCH v4 01/11] target/riscv: Add properties for Indirect CSR Access extension

Signed-off-by: Atish Patra Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f219f0c3b527..963f1f3af9ae 100644

Re: Subject: [PATCH] loader: Add register setting support via cli

On Wed, Jan 8, 2025 at 12:28 PM Sam Price wrote: > > I made the changes, and added documentation. > https://gitlab.com/thesamprice/qemu/-/compare/master...loader?from_project_id=11167699 > > I left it as [PREFIX] > > I can switch this to just RegNumber if desired. > > I am still struggling with th

Re: [PATCH v12 0/6] Add Smrnmi support

On Mon, Jan 6, 2025 at 3:46 PM wrote: > > From: Frank Chang > > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > ==

Re: [PATCH v12 5/6] target/riscv: Add Smrnmi cpu extension

: Daniel Henrique Barboza > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/tcg/tcg-cpu.c | 9 + > 2 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.c b/targe

Re: [PATCH v12 3/6] target/riscv: Handle Smrnmi interrupt and exception

sers to set the address based on their > expectation. This patch also adds the functionality to handle the RNMI > signals. > > Signed-off-by: Frank Chang > Signed-off-by: Tommy Wu > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/

Re: [PATCH v15 0/7] Pointer Masking update for Zjpm v1.0

On Mon, Jan 6, 2025 at 8:25 PM wrote: > > From: Alexey Baturo > > Hi, > > Rebased against Alistair's riscv-to-apply.next > > Thanks > > [v14]: > Rebased and addressed Alistair's comments on code style. > > > [v13]: > Rebased and addressed Daniel's comments about the return type of the helper. > >

Re: [PATCH v2 0/2] target/riscv: add traces for exceptions

On Tue, Jan 7, 2025 at 3:38 AM Daniel Henrique Barboza wrote: > > Hi, > > This new version is a re-sent of v1, rebased on top of > alistair/riscv-to-apply.next, with acks/r-bs added. > > No other changes made. > > Changes from v1: > - rebased on top of alistair/riscv-to-apply.next > - v1 link: >

Re: [PATCH] binfmt: Don't consider riscv{32, 64} part of the same family

On Tue, Jan 7, 2025 at 3:54 AM Andrea Bolognani wrote: > > On Mon, Jan 06, 2025 at 11:57:58AM +, Daniel P. Berrangé wrote: > > On Mon, Jan 06, 2025 at 11:47:00AM +, Peter Maydell wrote: > > > On Mon, 6 Jan 2025 at 01:29, Alistair Francis > > > wrote: >

Re: Subject: [PATCH] loader: Add register setting support via cli

system/generic-loader.rst Yes please > > Are unit tests needed? I think for now I wouldn't worry about it Alistair > Any guidance on what you would want done for this would be appreciated. > > Thanks, > Sam > > On Sun, Jan 5, 2025 at 11:41 PM Alistair Francis wrote:

Re: Subject: [PATCH] loader: Add register setting support via cli

On Fri, Dec 6, 2024 at 1:30 PM Sam Price wrote: > > I needed to set the registers prior to boot up to mimic what uboot > would do prior to loading a binary. This adds a generic option of reg > to the loader command, it uses the existing gcc commands for setting > register values. > > I'm sorry I

Re: [PATCH v11 0/6] Add Smrnmi support

On Tue, Dec 31, 2024 at 1:28 PM wrote: > > From: Frank Chang > > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > =

Re: [PATCH v11 6/6] target/riscv: Add Zicfilp support for Smrnmi

et, if the mnstatus.MNPP holds the > value y, then ELP is set to the value of MNPELP if yLPE is 1; > otherwise, it is set to NO_LP_EXPECTED. > > Signed-off-by: Frank Chang > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > tar

Re: [PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

On Tue, Dec 31, 2024 at 1:28 PM wrote: > > From: Tommy Wu > > This adds the properties for ISA extension Smrnmi. > > Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set > mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all > interrupts will be disabled. Since our cur

Re: [PATCH v11 4/6] target/riscv: Add Smrnmi mnret instruction

tion mode of the > interrupted context. > > Signed-off-by: Frank Chang > Signed-off-by: Tommy Wu > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 1 + > target/riscv/in

Re: [PATCH v14 0/7] Pointer Masking update for Zjpm v1.0

On Tue, Dec 17, 2024 at 6:57 PM wrote: > > From: Alexey Baturo > > Hi, > > Rebased and addressed Alistair's comments on code style. > > Thanks > > [v13]: > Rebased and addressed Daniel's comments about the return type of the helper. > > Thanks > > [v12]: > Rebased and addressed Richard's comments

Re: [PATCH 0/2] target/riscv: add traces for exceptions

On Fri, Dec 20, 2024 at 3:47 AM Daniel Henrique Barboza wrote: > > Hi, > > Let's add trace capabilities in riscv_raise_exception() to allow users > of qemu-riscv(32/64) to have a little more information when a SIGILL > occurs. This is done in patch 2. > > Patch 1 is a "look and feel" patch that I

Re: [PATCH v14 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

On Tue, Dec 17, 2024 at 6:57 PM wrote: > > From: Alexey Baturo > > Signed-off-by: Alexey Baturo > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h| 5 +++ > target

Re: [PATCH 2/2] target/riscv: add trace in riscv_raise_exception()

on 8 (user_ecall) on epc 0x17cd2 > riscv_exception 8 (user_ecall) on epc 0x17cda > riscv_exception 8 (user_ecall) on epc 0x17622 > (...) > riscv_exception 2 (illegal_instruction) on epc 0x1053a > Illegal instruction (core dumped) > > Signed-off-by: Daniel Henrique Barboza Re

Re: [PATCH 1/2] target/riscv: use RISCVException enum in exception helpers

gt; As a side effect, change 'excp' type from int to RISCVException in > generate_exception() to guarantee that all callers of > riscv_raise_exception() will use the enum. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/r

Re: [PATCH v2 0/9] target/riscv: add 'sha' support

On Wed, Dec 18, 2024 at 9:42 PM Daniel Henrique Barboza wrote: > > Hi, > > In this version the errors with 'bios-tables-test' qtest are fixed in > each patch that ended up breaking it. The test will break every time > we're changing the default riscv,isa DT from the 'rv64' CPU. > > This doesn't ha

Re: [PATCH v1 1/1] target/riscv: Fix handling of NOP for vstart >= vl in vext_vx_rm_2()

On Tue, Dec 17, 2024 at 6:46 PM Chao Liu wrote: > > fix: > https://lore.kernel.org/all/20240322085319.1758843-8-alistair.fran...@wdc.com/ Can you include a commit message of what this fixes? Instead of linking to the pull request there should be a fixes tag here, like this Fixes: df4252b2ecaf

Re: [PATCH v4] riscv/gdbstub: add V bit to priv reg

On Mon, Dec 16, 2024 at 7:38 AM Yanfeng Liu wrote: > > This adds virtualization mode (V bit) as bit(2) of register `priv` > per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. > > Note that GDB may display `INVALID` tag for `priv` reg when V bit > is set, this doesn't affect actual

Re: [PATCH v4] riscv/gdbstub: add V bit to priv reg

sn't affect actual access to the bit though. > > Signed-off-by: Yanfeng Liu Reviewed-by: Alistair Francis Alistair > --- > target/riscv/gdbstub.c | 23 +++ > 1 file changed, 19 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/gdbstub.c

Re: [PATCH v8 0/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores

lackm...@embecosm.com/ > - v7: > https://lore.kernel.org/all/20241211125113.583902-1-craig.blackm...@embecosm.com/ > > Cc: Richard Henderson > Cc: Palmer Dabbelt > Cc: Alistair Francis > Cc: Bin Meng > Cc: Weiwei Li > Cc: Daniel Henrique Barboza > Cc: Liu Zhiw

Re: [PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

On Tue, Dec 31, 2024 at 1:28 PM wrote: > > From: Tommy Wu > > Because the RNMI interrupt trap handler address is implementation defined. > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property > of the harts. It’s very easy for users to set the address based on their > ex

Re: [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register

On Wed, Dec 25, 2024 at 10:39 PM Ivan Klokov wrote: > > Added demo for reading CSR register from qtest environment. > > Signed-off-by: Ivan Klokov > Reviewed-by: Fabiano Rosas > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- >

Re: [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support

> > Signed-off-by: Ivan Klokov > Acked-by: Fabiano Rosas > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > hw/riscv/riscv_hart.c | 56 ++ > tests/qtest/libqtest.c | 27 +++

Re: [PATCH] binfmt: Don't consider riscv{32, 64} part of the same family

On Fri, Jan 3, 2025 at 2:04 AM Andrea Bolognani wrote: > > On Tue, Dec 03, 2024 at 10:47:02AM +0100, Andrea Bolognani wrote: > > Currently the script won't generate a configuration file that > > sets up qemu-user-riscv32 on riscv64, likely under the > > assumption that 64-bit RISC-V machines can n

Re: [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions

On Fri, Jan 3, 2025 at 4:21 AM Richard Henderson wrote: > > Signed-off-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- > tcg/riscv/tcg-target-has.h | 8 +++- > tcg/riscv/tcg-target.c.inc | 13 +++-- > 2 files changed, 18 insertions(+), 3 del

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