The following changes since commit 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5:
Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu into staging (2025-01-16 09:03:43 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250117-2 for you to fetch changes up to f195d4af294f76762407e2273a564950a8f42db6: hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events (2025-01-17 15:52:56 +1000) ---------------------------------------------------------------- Second RISC-V PR for 10.0 * Reduce the overhead for simple RISC-V vector unit-stride loads and stores * Add V bit to GDB priv reg * Add 'sha' support * Add traces for exceptions in user mode * Update Pointer Masking to Zjpm v1.0 * Add Smrnmi support * Fix timebase-frequency when using KVM acceleration * Add RISC-V Counter delegation ISA extension support * Add support for Smdbltrp and Ssdbltrp extensions * Introduce a translation tag for the IOMMU page table cache * Support Supm and Sspm as part of Zjpm v1.0 * Convert htif debug prints to trace events ---------------------------------------------------------------- Alexey Baturo (8): target/riscv: Remove obsolete pointer masking extension code. target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 target/riscv: Add helper functions to calculate current number of masked bits for pointer masking target/riscv: Add pointer masking tb flags target/riscv: Update address modify functions to take into account pointer masking target/riscv: Apply pointer masking for virtualized memory accesses target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension target/riscv: Support Supm and Sspm as part of Zjpm v1.0 Atish Patra (5): target/riscv: Enable S*stateen bits for AIA target/riscv: Add properties for counter delegation ISA extensions target/riscv: Invoke pmu init after feature enable target/riscv: Add implied rule for counter delegation extensions target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Clément Léger (9): target/riscv: Fix henvcfg potentially containing stale bits target/riscv: Add Ssdbltrp CSRs handling target/riscv: Implement Ssdbltrp sret, mret and mnret behavior target/riscv: Implement Ssdbltrp exception handling target/riscv: Add Ssdbltrp ISA extension enable switch target/riscv: Add Smdbltrp CSRs handling target/riscv: Implement Smdbltrp sret, mret and mnret behavior target/riscv: Implement Smdbltrp behavior target/riscv: Add Smdbltrp ISA extension enable switch Craig Blackmore (2): target/riscv: rvv: fix typo in vext continuous ldst function names target/riscv: rvv: speed up small unit-stride loads and stores Daniel Henrique Barboza (9): target/riscv: add shcounterenw target/riscv: add shvstvala target/riscv: add shtvala target/riscv: add shvstvecd target/riscv: add shvsatpa target/riscv: add shgatpa target/riscv/tcg: add sha target/riscv: use RISCVException enum in exception helpers target/riscv: add trace in riscv_raise_exception() Frank Chang (1): target/riscv: Add Zicfilp support for Smrnmi Jason Chien (1): hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache Kaiwen Xue (6): target/riscv: Add properties for Indirect CSR Access extension target/riscv: Decouple AIA processing from xiselect and xireg target/riscv: Support generic CSR indirect access target/riscv: Add counter delegation definitions target/riscv: Add select value range check for counter delegation target/riscv: Add counter delegation/configuration support Philippe Mathieu-Daudé (3): target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu hw/riscv/virt: Remove unnecessary use of &first_cpu hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events Tommy Wu (5): target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig target/riscv: Add Smrnmi CSRs target/riscv: Handle Smrnmi interrupt and exception target/riscv: Add Smrnmi mnret instruction target/riscv: Add Smrnmi cpu extension Yanfeng Liu (1): riscv/gdbstub: add V bit to priv reg include/hw/riscv/riscv_hart.h | 4 + target/riscv/cpu.h | 65 +- target/riscv/cpu_bits.h | 157 ++- target/riscv/cpu_cfg.h | 13 + target/riscv/helper.h | 1 + target/riscv/internals.h | 54 + target/riscv/kvm/kvm_riscv.h | 4 +- target/riscv/pmp.h | 1 + target/riscv/insn32.decode | 3 + hw/char/riscv_htif.c | 15 +- hw/riscv/riscv-iommu.c | 205 +++- hw/riscv/riscv_hart.c | 41 + hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 97 +- target/riscv/cpu_helper.c | 311 +++++- target/riscv/csr.c | 1257 +++++++++++++++++------- target/riscv/gdbstub.c | 23 +- target/riscv/kvm/kvm-cpu.c | 4 +- target/riscv/machine.c | 18 +- target/riscv/op_helper.c | 126 ++- target/riscv/pmp.c | 14 +- target/riscv/tcg/tcg-cpu.c | 50 +- target/riscv/translate.c | 49 +- target/riscv/vector_helper.c | 31 +- target/riscv/insn_trans/trans_privileged.c.inc | 20 + hw/char/trace-events | 4 + target/riscv/trace-events | 3 + tests/data/acpi/riscv64/virt/RHCT | Bin 332 -> 390 bytes 28 files changed, 1852 insertions(+), 720 deletions(-)
