On Tue, Jan 14, 2025 at 5:45 AM <baturo.ale...@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.ale...@gmail.com>
>
> Rebased against alistair/riscv-to-apply.next
>
> [v1]:
I removed the lines above, as we don't want to include the changelog
or rebase notes in the commit message
> The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are
> used in profile specification.
> Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only
> Smnpm.
>
> Signed-off-by: Alexey Baturo <baturo.ale...@gmail.com>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 23 +++++++++++++++++++++++
> target/riscv/cpu_cfg.h | 2 ++
> 2 files changed, 25 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index bddf1ba75e..3d4bd157d2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -208,10 +208,12 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind),
> ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp),
> ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
> + ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
> ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
> ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
> ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> + ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
> ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
> ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> @@ -1625,6 +1627,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
> MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
> MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
> + MULTI_EXT_CFG_BOOL("sspm", ext_sspm, false),
> + MULTI_EXT_CFG_BOOL("supm", ext_supm, false),
>
> MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
> MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false),
> @@ -2781,6 +2785,24 @@ static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule SUPM_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_supm),
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_ssnpm), CPU_CFG_OFFSET(ext_smnpm),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule SSPM_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_sspm),
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_smnpm),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> &RVM_IMPLIED, &RVV_IMPLIED, NULL
> @@ -2799,6 +2821,7 @@ RISCVCPUImpliedExtsRule
> *riscv_multi_ext_implied_rules[] = {
> &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
> &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
> &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
> + &SUPM_IMPLIED, &SSPM_IMPLIED,
> NULL
> };
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index aef896ba00..b410b1e603 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -139,6 +139,8 @@ struct RISCVCPUConfig {
> bool ext_ssnpm;
> bool ext_smnpm;
> bool ext_smmpm;
> + bool ext_sspm;
> + bool ext_supm;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
> bool rvv_vl_half_avl;
> --
> 2.39.5
>
>
