On Wed, Dec 4, 2024 at 9:16 AM Atish Patra <ati...@rivosinc.com> wrote: > > This adds the properties for counter delegation ISA extensions > (Smcdeleg/Ssccfg). Definitions of new registers and and implementation > will come in the next set of patches. > > Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Signed-off-by: Atish Patra <ati...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 963f1f3af9ae..82edd28e2e1d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -184,11 +184,13 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg), > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 8b974255f6fb..ae2b019703fe 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -78,6 +78,8 @@ struct RISCVCPUConfig { > bool ext_ztso; > bool ext_smstateen; > bool ext_sstc; > + bool ext_smcdeleg; > + bool ext_ssccfg; > bool ext_smcntrpmf; > bool ext_smcsrind; > bool ext_sscsrind; > > -- > 2.34.1 > >