On Wed, Dec 4, 2024 at 9:17 AM Atish Patra <ati...@rivosinc.com> wrote:
>
> The counter delegation/configuration extensions depend on the following
> extensions.
>
> 1. Smcdeleg - To enable counter delegation from M to S
> 2. S[m|s]csrind - To enable indirect access CSRs
>
> Add an implied rule so that these extensions are enabled by default
> if the sscfg extension is enabled.
>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 82edd28e2e1d..410ca2e3a666 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2642,6 +2642,16 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_ssccfg),
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_smcsrind), CPU_CFG_OFFSET(ext_sscsrind),
> + CPU_CFG_OFFSET(ext_smcdeleg),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> &RVM_IMPLIED, &RVV_IMPLIED, NULL
> @@ -2659,7 +2669,7 @@ RISCVCPUImpliedExtsRule
> *riscv_multi_ext_implied_rules[] = {
> &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
> &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
> &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
> - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
> + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
> NULL
> };
>
>
> --
> 2.34.1
>
>
