[PATCH v2] Support madvise(MADV_DONTDUMP) when creating core dumps for qemu-user

When running applications which make large (sparsely populated) address ranges (e.g. when using address sanitizer with LibAFL) the inability to exclude these regions from any core dump can result in very large files which fill the disk. A coredump is obvously very useful for performing a post-morte

Re [PATCH v3 08/11] mirror: Skip writing zeroes when target is already zero

On Thu, 1 May 2025 12:58:42 -0500, Eric wrote: > On Thu, May 01, 2025 at 12:38:30AM +0800, Sunny Zhu wrote: > > on Thu 24 Apr 2025 19:52:08 -0500, Eric wrote: > > > if (s->zero_target) { > > > +int64_t bitmap_length = DIV_ROUND_UP(s->bdev_length, > > > s->granularity); > > > + > > >

[PATCH v4 18/22] usb/msd: Rename mode to cbw_state, and tweak names

This reflects a little better what it does, particularly with a subsequent change to relax the order packets are seen in. This field is not the general state of the MSD state machine, rather it follows packets that are completed as part of a CBW command. The difference is a bit subtle, so for a co

[PATCH v4 08/22] tests/qtest/usb-hcd-xhci: Deliver msix interrupts

msix --- tests/qtest/usb-hcd-xhci-test.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c index 7f801f8f1a0..2eecc8d9f26 100644 --- a/tests/qtest/usb-hcd-xhci-test.c +++ b/tests/qtest/usb-hcd-xhci-t

[PATCH v4 21/22] tests/qtest/xhci: Test USB Mass Storage relaxed CSW order

This adds a qtest for the improvement to the MSD protocol that allows an IN packet before the CBW packet. Send a CSW packet before a zero-length CBW command packet is sent. This test would fail with the MSD change reverted. Signed-off-by: Nicholas Piggin --- tests/qtest/usb-hcd-xhci-test.c | 180

[PATCH v4 01/22] hw/usb/xhci: Move HCD constants to a header and add register constants

Prepare to use some of these constants in xhci qtest code. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci.h | 214 ++ hw/usb/hcd-xhci.c | 450 +++--- 2 files changed, 360 insertions(+), 304 deletions(-) diff --git a/hw/usb/hcd-xhci

[PATCH v4 15/22] usb/msd: Allow CBW packet size greater than 31

The CBW structure is 31 bytes, so CBW DATAOUT packets must be at least 31 bytes. QEMU enforces exactly 31 bytes, but this is inconsistent with how it handles CSW packets (where it allows greater than or equal to 13 bytes) despite wording in the spec[*] being similar for both packet types: "shall en

[PATCH v4 09/22] hw/usb/hcd-xhci-pci: Make PCI device more configurable

To prepare to support another USB PCI Host Controller, make some PCI configuration dynamic. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci-pci.h | 9 hw/usb/hcd-xhci-pci.c | 118 +- 2 files changed, 103 insertions(+), 24 deletions(-) diff --git

[PATCH v4 16/22] usb/msd: Split async packet tracking into data and csw

The async packet handling logic has places that infer whether the async packet is data or CSW, based on context. This is not wrong, it just makes the logic easier to follow if they are categorised when they are accepted. Signed-off-by: Nicholas Piggin --- include/hw/usb/msd.h | 5 +- hw/usb/de

Re: [PATCH v3 07/11] mirror: Skip pre-zeroing destination if it is already zero

On Thu, 1 May 2025 12:33:14 -0500, Eric wrote: > > > + * If the destination already reads as zero, and we are not > > > + * requested to punch holes into existing zeroes, then we can > > > + * skip pre-zeroing the destination. > > > + */ > > > +if (ret > 0 &&

[PATCH v4 22/22] usb/msd: Add more tracing

Add tracing for more received packet types, cbw_state changes, and some more SCSI callbacks. These were useful in debugging relaxed packet ordering support. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- hw/usb/dev-storage.c | 61 +

[PATCH v4 07/22] tests/qtest/xhci: add a test for TR NOOP commands

Run some TR NOOP commands through the transfer ring. Signed-off-by: Nicholas Piggin --- tests/qtest/usb-hcd-xhci-test.c | 36 + 1 file changed, 36 insertions(+) diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c index 39c5c36e940..7f80

[PATCH v4 19/22] usb/msd: Add NODATA CBW state

This is not really required for the state machine but it improves the symmetry of zero-data packets with data packets, and helps with assertions and reasoning about traces. Signed-off-by: Nicholas Piggin --- include/hw/usb/msd.h | 1 + hw/usb/dev-storage.c | 10 +++--- 2 files changed, 8 in

[PATCH v4 14/22] usb/msd: Improve packet validation error logging

Errors in incoming USB MSD packet format or context would typically be guest software errors. Log these under guest errors. Signed-off-by: Nicholas Piggin --- hw/usb/dev-storage.c | 53 +++- 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/h

[PATCH v4 13/22] usb/msd: Improved handling of mass storage reset

The mass storage reset request handling does not reset in-flight SCSI requests or USB MSD packets. Implement this by calling the device reset handler which should take care of everything. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- hw/usb/dev-storage.c | 2 +- 1 file

[PATCH v4 17/22] usb/msd: Add some additional assertions

Add more assertions to help verify internal logic. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- hw/usb/dev-storage.c | 23 +++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c index 66fffda37

[PATCH v4 12/22] usb/msd: Ensure packet structure layout is correct

These structures are hardware interfaces, ensure the layout is correct. Add defines for the data sizes throughout the code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- hw/usb/dev-storage.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) d

[PATCH v4 02/22] hw/usb/xhci: Rename and move HCD register region constants to header

This also adds some missing constants rather than open-coding offsets and sizes. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci.h | 16 hw/usb/hcd-xhci.c | 48 ++- 2 files changed, 38 insertions(+), 26 deletions(-) diff --git a/hw

[PATCH v4 20/22] usb/msd: Permit a DATA-IN or CSW packet before CBW packet

The USB MSD protocol has 3 packets that make up a command, and only one command may be active at any time. - CBW to start a command (that contains a SCSI request). - DATA (IN or OUT) to request data transfer between host and SCSI layer. - CSW to return status and complete the command. DATA is omi

[PATCH v4 04/22] tests/qtest/xhci: Add controller and device setup and ring tests

Add tests which init the host controller registers to the point where command and event rings, irqs are operational. Enumerate ports and set up an attached device context that enables device transfer ring to be set up and tested. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci.h

[PATCH v4 03/22] tests/qtest/xhci: test the qemu-xhci device

Add support in the test code for running multiple drivers, and add tests for the qemu-xhci device. Signed-off-by: Nicholas Piggin --- tests/qtest/usb-hcd-xhci-test.c | 190 +--- 1 file changed, 176 insertions(+), 14 deletions(-) diff --git a/tests/qtest/usb-hcd-xhci-

[PATCH v4 11/22] usb/msd: Split in and out packet handling

Split in and out packet handling int otheir own functions, to make them a bit more managable. Signed-off-by: Nicholas Piggin --- hw/usb/dev-storage.c | 266 +++ 1 file changed, 145 insertions(+), 121 deletions(-) diff --git a/hw/usb/dev-storage.c b/hw/usb

[PATCH v4 06/22] hw/usb/xhci: Support TR NOOP commands

Implement XHCI TR NOOP commands by setting up then immediately completing the packet. The IBM AIX XHCI HCD driver uses NOOP commands to check driver and hardware health, which works after this change. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci.c | 28 +++- 1 file

[PATCH v4 05/22] tests/qtest/xhci: Add basic USB Mass Storage tests

Add a usb-storage device to xhci tests, enable USB Mass Storage Bulk endpoints, and run some MSD commands through it. Signed-off-by: Nicholas Piggin --- tests/qtest/usb-hcd-xhci-test.c | 359 +++- 1 file changed, 351 insertions(+), 8 deletions(-) diff --git a/tests/q

[PATCH v4 10/22] hw/usb/hcd-xhci-pci: Add TI TUSB73X0 XHCI controller model

The TI TUSB73X0 controller has some interesting differences from NEC, notably a separate BAR for MSIX, and PM capabilities. The spec is freely available without sign-up. This controller is accepted by IBM Power proprietary firmware and software (when the subsystem IDs are set to Power servers, whi

[PATCH v4 00/22] usb/xhci and usb/msd improvements and tests

This is merged from two series now because code especially the test cases have started to depend on one another. The series are "usb/xhci: TR NOOP, TI HCD device, more qtests" from: https://lore.kernel.org/qemu-devel/20250411080431.207579-1-npig...@gmail.com/ And "usb/msd: Permit relaxed ordering

[PATCH v3 02/12] net/e1000e: Permit disabling interrupt throttling

The spec explicitly permits xITR register interval field to have a value of zero to disable throttling. The e1000e model already allows for this in the throttling logic, so remove the minimum value for the register. The spec appears to say there is a maximum observable interrupt rate when throttli

[PATCH v3 11/12] net/e1000e|igb: Fix interrupt throttling rearming

Timer expiry that results in an interrupt does not rearm the timer so an interrupt can appear immediately after the interrupt generated by timer expiry. Fix this by rearming the throttle timer when a delayed interrupt is processed. e1000e gets this by reusing the e1000e_msix_notify() logic, igb ca

[PATCH v3 04/12] qtest/e1000e|igb: assert irqs are clear before triggering an irq

Assert there is no existing irq raised that would lead to a false positive interrupt test. e1000e has to disable interrupt throttling for this test, because it can cause delayed superfluous interrupts which trip the assertions. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Dmitry Fleytman Cc

[PATCH v3 12/12] qtest/e1000e|igb: Test interrupt throttling in multiple_transfers test

Enable interrupt throtling on one of the two queue interrupts used in the multiple_transfers test, to improve coverage. The number of interrupts for the e1000e test is reduced because it has a long minimum throttling delay so without reducing iterations throttling adds about 40s to the test runtime

[PATCH v3 09/12] hw/net/e1000e: Do not auto-clear cause on postponed msix interrupt

If an interrupt is postponed, it should not do cause auto-clearing or auto-masking. That is done when the interrupt processing occurs. Signed-off-by: Nicholas Piggin --- hw/net/e1000e_core.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/

[PATCH v3 08/12] hw/net/e1000e: Postponed msix interrupt processing should auto-clear cause

Cause auto-clearing and masking should be performed during msix interrupt processing. Signed-off-by: Nicholas Piggin --- hw/net/e1000e_core.c | 86 +++- 1 file changed, 69 insertions(+), 17 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_co

[PATCH v3 10/12] net/e1000e|igb: Only send delayed msix interrupts that have a cause

The msix interrupt throttling timer expiry sends an interrupt even if there is no unmasked interrupt causes. This can be observed by seeing two interrupts in response to a single event when throttling is active. The e1000e non-msix paths seem to get this right by masking and testing ICR and IMS. A

[PATCH v3 07/12] igb: Add a note about re-loading timers breaking deterministic replay

Add a note about the problem re-loading timers with default values. Deterministic replay requires the timers be migrated with the same value. Signed-off-by: Nicholas Piggin --- hw/net/igb_core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/net/igb_core.c b/hw/net/igb

[PATCH v3 06/12] net/igb: Implement EITR Moderation Counter

IGB EITR registers have counter fields which reflect the current ITR and LLI counter values, as well as a bit to enable LLI moderation, and a bit to write the register without modifying the counter fields. Implement the EITR Moderation Counter (aka EITR counter), and counter ignore bit. The EITR c

[PATCH v3 03/12] hw/net/e1000e|igb: Remove xitr_guest_value logic

The guest value xITR logic is not required now that the write functions store necessary data to be read back, and internal users mask and shift fields they need as they go. Signed-off-by: Nicholas Piggin --- hw/net/e1000e_core.c | 31 +++ hw/net/igb_core.c| 16 +++

[PATCH v3 05/12] net/igb: Fix interrupt throttling interval calculation

IGB throttling granularity is 1us, and interval field is in bits 2..14 of the EITRx registers. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Nicholas Piggin --- hw/net/igb_regs.h | 3 +++ hw/net/igb_core.c | 7 --- 2 files changed, 7 insertions(+), 3 deletions(-) dif

[PATCH v3 00/12] hw/e1000e|igb: interrupts and qtests fixes

Since v2: https://lore.kernel.org/qemu-devel/20250411043128.201289-1-npig...@gmail.com/ Mostly fixed comments from Akihiko Odaki - e1000e change initial ITR as well as EITR - Preserve EITR writable bits - Use SCALE_US constant instead of 1000 - Fix register field definitions to not trample on cod

[PATCH v3 01/12] qtest/e1000e|igb: Clear interrupt-cause and msix pending bits after irq

The e1000e and igb tests do not clear the ICR/EICR cause bits (or set auto-clear) on seeing queue interrupts, which inhibits the triggering of a new interrupt. The msix pending bit which is used to test for the interrupt is also not cleared (the vector is masked). Fix this by clearing the ICR/EICR

[PATCH v5 11/11] qtest/libqos/pci: Factor msix entry helpers into pci common code

Setting msix entry address and data and masking is moved into common code helpers from virtio tests. For now that remains the only user, but there are changes under development to enable msix vectors for msix, e1000e, and xhci tests, which can make use of them. Reviewed-by: Akihiko Odaki Signed-

[PATCH v5 10/11] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0

Devices where the MSI-X addresses are shared with other MMIO on BAR0 can not use msi_enable because it unmaps and remaps BAR0, which interferes with device MMIO mappings. xhci-nec is one such device we would like to test with msix. Use the BAR iomap tracking structure introduced in the previous ch

[PATCH v5 05/11] tests/qtest/ahci: unmap pci bar before reusing device

ahci-test double-maps the hba bar in the pending_callback test. Unmap it first, to keep iomaps balanced. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Akihiko Odaki Reviewed-by: Akihiko Odaki Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/ahci.h | 2 ++

[PATCH v5 06/11] tests/qtest/ahci: don't unmap pci bar if it wasn't mapped

ahci-test has a bunch of tests where the pci bar was not mapped. Avoid unmapping it in these cases, to keep iomaps balanced. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Akihiko Odaki Cc: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/ahci.h | 1 + tests/qtest/ahci-te

[PATCH v5 04/11] tests/qtest: Enable spapr dma with linear iommu map

qtests spapr dma was broken because the iommu was not set up. spapr requires hypercalls to set up the iommu (TCE tables), but there is no support for that or a side-channel to the iommu in qtests at the moment, so add a quick workaround in QEMU to have the spapr iommu provide a linear map to memor

[PATCH v5 02/11] tests/qtest: Fix virtio msix message endianness

msix messages are written to memory in little-endian order, so they should not be byteswapped depending on target endianness, but read as le and converted to host endian by the qtest. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/

[PATCH v5 08/11] tests/qtest/libquos/pci: Add migration fixup helper for pci devices

Migration tests can create new QPCI devices for the destination machine which may need to take on some state of the source machine after destination is complete. Add a migration fixup helper and call it from ahci migration tests. This is currently a noop and will be used subsequently. Reviewed-by

[PATCH v5 09/11] qtest/libqos/pci: Enforce balanced iomap/unmap

Add assertions to ensure a BAR is not mapped twice, and that only previously mapped BARs are unmapped. This can help catch bugs and fragile coding. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Reviewed-by: Akihiko Odaki Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest

[PATCH v5 07/11] tests/qtest/libquos/virtio: unmap pci bar when disabling device

Unmap the virtio-pci bar in qvirtio_pci_disable_device() to keep iomap/iounmap balanced. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Reviewed-by: Akihiko Odaki Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/virtio-pci.h | 1 + tests/qtest/libqos/virtio-pci.

[PATCH v5 03/11] tests/qtest: Add libqos function for testing msix interrupt status

This function is duplicated 3 times, with more potential future users. Factor it into libqos, using qtest_memset instead of qtest_writel to clear the message just because that looks nicer with the qtest_memread used to read it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin -

[PATCH v5 01/11] tests/qtest: Enforce zero for the "un-fired" msix message value

virtio-pci detects an unmasked msix interrupt has fired by looking for the data payload value at the target address. If a value of zero is enforced for the memory value when an interrupt has not fired, then an assertion can be added to catch the case where something changed the memory to an unexpec

[PATCH v5 00/11] tests/qtest: pci and msix fixes

Since v4: https://lore.kernel.org/qemu-devel/20250411044130.201724-1-npig...@gmail.com/ I merged in the "spapr" series that touches similar code: https://lore.kernel.org/qemu-devel/20250416145918.415674-1-npig...@gmail.com/ - Simplified the ahci shutdown logic to keep one unified shutdown func

[PATCH v2 09/20] amd_iommu: Add basic structure to support IOMMU notifier updates

Add the minimal data structures required to maintain a list of address spaces (i.e. devices) with registered notifiers, and to update the type of events that require notifications. Note that the ability to register for MAP notifications is not available. It will be unblocked by following changes th

[PATCH v2 20/20] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk

Simplify amdvi_page_walk() by making it call the fetch_pte() helper that is already in use by the shadow page synchronization code. Ensures all code uses the same page table walking algorithm. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 59 +

[PATCH v2 12/20] amd_iommu: Unmap all address spaces under the AMD IOMMU on reset

Support dropping all existing mappings on reset. When the guest kernel reboots it will create new ones, but other components that run before the kernel (e.g. OVMF) should not be able to use existing mappings from the previous boot. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 74 ++

[PATCH v2 00/20] AMD vIOMMU: DMA remapping support for VFIO devices

This series adds support for guests using the AMD vIOMMU to enable DMA remapping for VFIO devices. In addition to the currently supported passthrough (PT) mode, guest kernels are now able to to provide DMA address translation and access permission checking to VFs attached to paging domains, using t

[PATCH v2 02/20] amd_iommu: Document '-device amd-iommu' common options

Document the common parameters used when emulating AMD vIOMMU. Besides the two amd-iommu specific options: 'xtsup' and 'dma-remap', the the generic x86 IOMMU option 'intremap' is also included, since it is typically specified in QEMU command line examples and mailing list threads. Signed-off-by: A

[PATCH v2 15/20] amd_iommu: Toggle memory regions based on address translation mode

Enable the appropriate memory region for an address space depending on the address translation mode selected for it. This is currently based on a generic x86 IOMMMU property, and only done during the address space initialization. Extract the code into a helper and toggle the regions based on whethe

[PATCH v2 13/20] amd_iommu: Add replay callback

A replay() method is necessary to efficiently synchronize the host page tables after VFIO registers a notifier for IOMMU events. It is called to ensure that existing mappings from an IOMMU memory region are "replayed" to a specified notifier, initializing or updating the shadow page tables on the h

[PATCH v2 17/20] amd_iommu: Add dma-remap property to AMD vIOMMU device

In order to enable device assignment with IOMMU protection and guest DMA address translation, IOMMU MAP notifier support is necessary to allow users like VFIO to synchronize the shadow page tables i.e. to receive notifications when the guest updates its I/O page tables and replay the mappings onto

[PATCH v2 19/20] amd_iommu: Do not assume passthrough translation when DTE[TV]=0

The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V, TV, and GV Fields in Device Table Entry), specifies that a DTE with V=1, TV=0 does not contain a valid address translation information. If a request requires a table walk, the walk is terminated when this condition is enco

[PATCH v2 11/20] amd_iommu: Use iova_tree records to determine large page size on UNMAP

Keep a record of mapped IOVA ranges per address space, using the iova_tree implementation. Besides enabling optimizations like avoiding unnecessary notifications, a record of existing mappings makes it possible to determine if a specific IOVA is mapped by the guest using a large page, and adjust t

[PATCH v2 01/20] memory: Adjust event ranges to fit within notifier boundaries

Invalidating the entire address space (i.e. range of [0, ~0ULL]) is a valid and required operation by vIOMMU implementations. However, such invalidations currently trigger an assertion unless they originate from device IOTLB invalidations. Although in recent Linux guests this case is not exercised

[PATCH v2 06/20] amd_iommu: Return an error when unable to read PTE from guest memory

Make amdvi_get_pte_entry() return an error value (-1) in cases where the memory read fails, versus the current return of 0 to indicate failure. The reason is that 0 is also a valid PTE value, and it is useful to know when a PTE points to memory that is zero i.e. the guest unmapped the page. Signed

[PATCH v2 16/20] amd_iommu: Set all address spaces to default translation mode on reset

On reset, restore the default address translation mode for all the address spaces managed by the vIOMMU. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 28 1 file changed, 28 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 7101

[PATCH v2 10/20] amd_iommu: Sync shadow page tables on page invalidation

When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the address and size of the invalidation and sync the guest page table state with the host. This requires walking the guest page table and calling notifiers registered for address spaces matching the domain ID encoded in the command.

[PATCH v2 05/20] amd_iommu: Add helper function to extract the DTE

Extracting the DTE from a given AMDVIAddressSpace pointer structure is a common operation required for syncing the shadow page tables. Implement a helper to do it and check for common error conditions. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 45

[PATCH v2 14/20] amd_iommu: Invalidate address translations on INVALIDATE_IOMMU_ALL

When the kernel IOMMU driver issues an INVALIDATE_IOMMU_ALL, the address translation and interrupt remapping information must be cleared for all Device IDs and all domains. Introduce a helper to sync the shadow page table for all the address spaces with registered notifiers, which replays both MAP

[PATCH v2 07/20] amd_iommu: Add helpers to walk AMD v1 Page Table format

The current amdvi_page_walk() is designed to be called by the replay() method. Rather than drastically altering it, introduce helpers to fetch guest PTEs that will be used by a page walker implementation. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 123

[PATCH v2 04/20] amd_iommu: Helper to decode size of page invalidation command

The size of the region to invalidate depends on the S bit and address encoded in the command. Add a helper to extract this information, which will be used to sync shadow page tables in upcoming changes. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 34 +++

[PATCH v2 18/20] amd_iommu: Toggle address translation mode on devtab entry invalidation

A guest must issue an INVALIDATE_DEVTAB_ENTRY command after changing a Device Table entry (DTE) e.g. after attaching a device and setting up its DTE. When intercepting this event, determine if the DTE has been configured for paging or not, and toggle the appropriate memory regions to allow DMA addr

[PATCH v2 08/20] amd_iommu: Add a page walker to sync shadow page tables on invalidation

For the specified address range, walk the page table identifying regions as mapped or unmapped and invoke registered notifiers with the corresponding event type. Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 75 + 1 file changed, 75 insert

[PATCH v2 03/20] amd_iommu: Reorder device and page table helpers

Move code related to Device Table and Page Table to an earlier location in the file, where it does not require forward declarations to be used by the various invalidation functions that will need to query the DTE and walk the page table in upcoming changes. This change consist of code movement onl

RE: [PATCH v3 5/9] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

Hi Cédric, > -Original Message- > From: Cédric Le Goater > Sent: Wednesday, April 30, 2025 5:46 PM > To: Steven Lee ; Peter Maydell > ; Troy Lee ; Jamin Lin > ; Andrew Jeffery > ; Joel Stanley ; open > list:ASPEED BMCs ; open list:All patches CC here > > Cc: Troy Lee ; long...@lenovo.com

RE: [PATCH v3 8/9] tests/function/aspeed: Add functional test for AST2700FC

Hi Cédric, > -Original Message- > From: Cédric Le Goater > Sent: Wednesday, April 30, 2025 5:35 PM > To: Steven Lee ; Peter Maydell > ; Troy Lee ; Jamin Lin > ; Andrew Jeffery > ; Joel Stanley ; open > list:ASPEED BMCs ; open list:All patches CC here > > Cc: Troy Lee ; long...@lenovo.com

RE: [PATCH v3 0/9] Introduce AST27x0 multi-SoC machine

Hi Cédric, > -Original Message- > From: Cédric Le Goater > Sent: Wednesday, April 30, 2025 5:31 PM > To: Steven Lee ; Peter Maydell > ; Troy Lee ; Jamin Lin > ; Andrew Jeffery > ; Joel Stanley ; open > list:ASPEED BMCs ; open list:All patches CC here > > Cc: Troy Lee ; long...@lenovo.com

[PATCH] hw/char/serial: Remove unused prog_if compat property

This property was added to preserve previous value when this was fixed in version 2.1 but the 2.0 machine using it was already removed leaving this property unused and unnecessary. This was also copy & pasted into diva-gsp where it was probably never used so get rid of this property at last. Fixes

Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros

On Mon, 28 Apr 2025, Pierrick Bouvier wrote: On 4/28/25 6:10 PM, BALATON Zoltan wrote: On Mon, 28 Apr 2025, Pierrick Bouvier wrote: On 4/28/25 11:44 AM, BALATON Zoltan wrote: On Mon, 28 Apr 2025, Pierrick Bouvier wrote: On 4/28/25 3:31 AM, BALATON Zoltan wrote: Since you are touching the lin

Re: [PATCH] Support madvise(MADV_DONTDUMP) when creating core dumps for qemu-user

On Thu, 1 May 2025, Jon Wilson wrote: Awesome. Thanks. How do I do that? Sorry I'm new to this workflow. Can you point me at a reference? qemu.org -> Contribute -> Patch submission guidelines: https://www.qemu.org/docs/master/devel/submitting-a-patch.html Regards, BALATON Zoltan

[PATCH 11/13] hw/ppc/pegasos2: Add bus frequency to machine state

Store the bus frequency in the machine state and set it from instance init method. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 25 - 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index f7999520e4..ae3f01231d

[PATCH 10/13] hw/ppc/pegasos2: Introduce abstract superclass

Rename machine state struct to PegasosMachineState as it will be used for pegasos1 too. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 66 --- 1 file changed, 34 insertions(+), 32 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c

[PATCH 09/13] hw/ppc/pegasos2: Move hardware specific parts out of machine reset

Move the chipset reset which is pegasos2 specific out from machine reset to a separate function and move parts not specific to pegasos2 form build_fdt in machine reset so now build_fdt contains pegasos2 specific parts and renamed accordingly. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c |

[PATCH 13/13] hw/ppc/pegasos2: Add VOF support for pegasos1

When running without firmware ROM using Virtual Open Firmware we need to do some hardware initialisation and provide the device tree as the machine firmware would normally do. Signed-off-by: BALATON Zoltan --- MAINTAINERS | 1 + hw/ppc/pegasos2.c| 140 +

[PATCH 12/13] hw/ppc/pegasos2: Add Pegasos I emulation

The Pegasos II is a redesign of the original Pegasos (later marked I) that replaces the north bridge and has updated firmware but otherwise these are very similar. The Pegasos uses the same north bridge that AmigaOne used which we already emulate so we can also easily emulate Pegasos I. Signed-off

[PATCH 08/13] hw/ppc/pegasos2: Move PCI IRQ routing setup to a function

Collect steps of setting up PCI IRQ routing in one function. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 66 +++ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 66bceec5ef..26a571f82

[PATCH 06/13] hw/ppc/pegasos2: Rename mv field in machine state

Use more generic name for the field used to store the north bridge in the machine state. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 7dc7803c64..9b50cd3d

[PATCH 03/13] hw/ppc/pegasos2: Remove explicit name properties from device tree

These are not needed any more now that VOF can handle it. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 17 - 1 file changed, 17 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index e15cf96427..73995624e5 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegas

[PATCH 02/13] ppc/vof: Make nextprop behave more like Open Firmware

The FDT does not normally store name properties but reconstructs it from path but Open Firmware specification says each node should at least have this property. This is correctly handled in getprop but nextprop should also return it even if not present as a property. Explicit name properties are s

[PATCH 04/13] hw/ppc/pegasos2: Change device tree generation

We generate a flattened device tree programmatically for VOF. Change this to load the static parts from a device tree blob and only generate the parts that depend on run time conditions such as CPU type, memory size and PCI devices. Moving the static parts in a dts makes the board code simpler and

[PATCH 05/13] hw/ppc/pegasos2: Remove fdt pointer from machine state

The machine class has a field for storing the fdt so we don't need our own and can use that instead. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 646755a3cc..7dc7803c64 1

[PATCH 00/13] Pegasos2 clean up and pegasos1 emulation

This series changes how the fdt for VOF is generated in pegasos2 by moving the static parts to a dtb and only generate the changing parts such as memory size and PCI devices programmatically. This simplifies the code and allows simply adding emulation of Pegasos I which has a different north bridge

[PATCH 07/13] hw/ppc/pegasos2: Add south bridge pointer in the machine state

Add field for the south bridge in machine state to have both north and south bridges in it. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 9b50cd3dab..66bceec5ef 100644 --- a/h

[PATCH 01/13] hw/boards: Extend DEFINE_MACHINE macro to cover more use cases

Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler versions with less parameters based on that. This is inspired by how the OBJECT_DEFINE macros do this in a similar way to allow using the shortened definition in more complex cases too. Signed-off-by: BALATON Zoltan --- include/

[PATCH 03/10] hw/input/virtio-input: Remove VirtIOInputHID::wheel_axis field

The VirtIOInputHID::wheel_axis boolean was only set in the hw_compat_2_10[] array, via the 'wheel-axis=false' property. We removed all machines using that array, lets remove that property and all the code around it. There is only one virtio_input_config[] version for each device, rename it removing

[PATCH 06/10] hw/net/e1000: Remove unused E1000_FLAG_TSO flag

E1000_FLAG_TSO was only used by the hw_compat_2_11[] array, via the 'migrate_tso_props=off' property. We removed all machines using that array, lets remove all the code around E1000_FLAG_TSO, including the vmstate_e1000_tx_tso_state subsection. Signed-off-by: Philippe Mathieu-Daudé --- Is it OK t

[PATCH 10/10] hw/display/vga-pci: Do not expose the 'global-vmstate' property

The "global-vmstate" property is 'false' by default, and was only set to 'true' in the hw_compat_2_12[] array. We removed all machines using that array. Stop exposing that property on the PCI devices. Signed-off-by: Philippe Mathieu-Daudé --- hw/display/cirrus_vga.c | 2 -- hw/display/qxl.c

[PATCH 08/10] hw/core/machine: Remove hw_compat_2_12[] array

The hw_compat_2_12[] array was only used by the pc-q35-2.12, pc-i440fx-2.12 and s390-ccw-virtio-2.12 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 3 --- hw/core/machine.c | 9 - 2 files changed, 12 deletions(-) diff --git a/in

[PATCH 00/10] hw/core: Remove hw_compat[] array for 2.10, 2.11 and 2.12 machines

Include Thomas s390x patches from [1], with the other x86 machines removal in [2], 3 hw_compat[] arrays end unused. Remove them, including unused properties. [1] https://lore.kernel.org/qemu-devel/20250115073819.15452-1-th...@redhat.com/ [2] https://lore.kernel.org/qemu-devel/20250501223522.99772-

[PATCH 05/10] hw/timer/hpet: Remove HPETState::hpet_offset_saved field

The HPETState::hpet_offset_saved boolean was only set in the hw_compat_2_11[] array, via the 'hpet-offset-saved=false' property. We removed all machines using that array, lets remove that property and all the code around it. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/hpet.c

[PATCH 09/10] hw/audio/hda-codec: Remove HDAAudioState::use_timer field

The HDAAudioState::use_timer boolean was only set in the hw_compat_2_12[] array, via the 'use-timer=false' property. We removed all machines using that array, lets remove that property and all the code around it, like the compatibility callbacks. Signed-off-by: Philippe Mathieu-Daudé --- hw/audi

[PATCH 02/10] hw/core/machine: Remove hw_compat_2_10[] array

The hw_compat_2_10[] array was only used by the pc-q35-2.10, pc-i440fx-2.10 and s390-ccw-virtio-2.10 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 3 --- hw/core/machine.c | 6 -- 2 files changed, 9 deletions(-) diff --git a/includ

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