IGB EITR registers have counter fields which reflect the current ITR
and LLI counter values, as well as a bit to enable LLI moderation,
and a bit to write the register without modifying the counter fields.
Implement the EITR Moderation Counter (aka EITR counter), and counter
ignore bit. The EITR counter is the time remaining in the interrupt
moderation delay which is implemented as a QEMU timer.
Log an unimp message if software tries to enable LLI moderation.
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
hw/net/igb_regs.h | 6 ++++++
hw/net/igb_core.c | 48 +++++++++++++++++++++++++++++++++++++++++------
2 files changed, 48 insertions(+), 6 deletions(-)
diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h
index a87aa44f5f3..c4785eda0ce 100644
--- a/hw/net/igb_regs.h
+++ b/hw/net/igb_regs.h
@@ -631,6 +631,12 @@ union e1000_adv_rx_desc {
#define E1000_EICR_MSIX_MASK 0x01FFFFFF /* Bits used in MSI-X mode */
#define E1000_EICR_LEGACY_MASK 0x4000FFFF /* Bits used in non MSI-X mode */
+/* These are only for 82576 and newer */
+#define E1000_EITR_INTERVAL 0x00007FFC
+#define E1000_EITR_LLI_EN 0x00008000
+#define E1000_EITR_LLI_CNT 0x001F0000
+#define E1000_EITR_ITR_CNT 0x7FE00000
+
/* Mirror VF Control (only RST bit); RW */
#define E1000_PVTCTRL(_n) (0x10000 + (_n) * 0x100)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 9e9e6e3354f..eedc341f298 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -140,12 +140,8 @@ static void igb_msix_notify(IGBCore *core, unsigned int
cause)
}
static inline void
-igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
+igb_intrmgr_arm_timer(IGBIntrDelayTimer *timer, int64_t delay_ns)
{
- int64_t delay_ns =
- (int64_t)((timer->core->mac[timer->delay_reg] & 0x7FFC) >> 2) *
- timer->delay_resolution_ns;
-
trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
@@ -153,6 +149,16 @@ igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
timer->running = true;
}
+static inline void
+igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
+{
+ uint32_t interval = (timer->core->mac[timer->delay_reg] &
+ E1000_EITR_INTERVAL) >> 2;
+ int64_t delay_ns = (int64_t)interval * timer->delay_resolution_ns;
+
+ igb_intrmgr_arm_timer(timer, delay_ns);
+}
+
static void
igb_intmgr_timer_resume(IGBIntrDelayTimer *timer)
{
@@ -2881,7 +2887,21 @@ igb_mac_swsm_read(IGBCore *core, int index)
static uint32_t
igb_mac_eitr_read(IGBCore *core, int index)
{
- return core->mac[index - EITR0];
+ uint32_t eitr_num = index - EITR0;
+ uint32_t val = core->mac[eitr_num];
+ IGBIntrDelayTimer *timer = &core->eitr[eitr_num];
+
+ if (timer->running) { /* timer is pending, find time remaining */
+ int64_t remains = timer_expire_time_ns(timer->timer) -
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ if (remains > 0) {
+ uint32_t cnt; /* CNT is the most significant 10 of 12 bits */
+ cnt = remains / timer->delay_resolution_ns;
+ val |= ((cnt >> 2) << 21) & E1000_EITR_ITR_CNT;
+ }
+ }
+
+ return val;
}
static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index)
@@ -3047,6 +3067,22 @@ igb_set_eitr(IGBCore *core, int index, uint32_t val)
trace_igb_irq_eitr_set(eitr_num, val);
+ if (val & (E1000_EITR_LLI_EN | E1000_EITR_LLI_CNT)) {
+ qemu_log_mask(LOG_UNIMP, "%s: LLI moderation not supported,
ignoring\n",
+ __func__);
+ }
+
+ if (!(val & E1000_EITR_CNT_IGNR)) {
+ IGBIntrDelayTimer *timer = &core->eitr[eitr_num];
+ uint32_t itr_cnt = (val & E1000_EITR_ITR_CNT) >> 21;
+ /* CNT is the most significant 10 of 12 bits */
+ uint64_t ns = (itr_cnt << 2) * timer->delay_resolution_ns;
+
+ igb_intrmgr_arm_timer(timer, ns);
+ }
+
+ val &= E1000_EITR_INTERVAL | E1000_EITR_LLI_EN;
+
core->mac[index] = val;
}
--
2.47.1
