Hi Clement,
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for
>scalable modern mode
>
>Hi zhenzhong,
>Just one comment but you can add Reviewed-by: Clément Mathieu--
>Drif
>
>
>On 11/11/2024 09:34, Zhenzhong Duan w
Removal was scheduled for 10.0. Use the rainier-bmc machine or the
ast2600-evb as a replacement.
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 8
docs/about/removed-features.rst | 10 ++
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c
Hi Eric,
>-Original Message-
>From: Eric Auger
>Sent: Tuesday, November 19, 2024 2:00 AM
>Subject: Re: nested-smmuv3 topic for QEMU/libvirt, Nov 2024
>
>Hi Nicolin,
>
>On 11/7/24 21:31, Nicolin Chen wrote:
>> Hi Eric,
>>
>> On Thu, Nov 07, 2024 at 12:11:05PM +0100, Eric Auger wrote:
>>> O
Hi zhenzhong,
Just one comment but you can add Reviewed-by: Clément
Mathieu--Drif
On 11/11/2024 09:34, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Intel VT-d 3.0 in
On Thu, Nov 14, 2024 at 7:16 PM Clément Léger wrote:
>
> Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
> {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
> presence of the Ssdbltrp ISA extension.
>
> Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
A
The following patches are queued for QEMU stable v9.1.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.1
Patch freeze is 2024-11-18 (today), and the release is planned for 2024-11-20:
https://wiki.qemu.org/Planning/9.1
Please respond here or CC qemu-sta...@nongnu.org on any addit
From: Richard Henderson
This path is reachable with plugins enabled, and provoked
with run-plugin-catch-syscalls-with-libinline.so.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-ID: <20241112141232.321354-1-richard.hender...@linaro.org>
(cherry
From: "Maciej S. Szmigiero"
Currently, ram_save_complete() sends a final SYNC multifd packet near this
function end, after sending all of the remaining RAM data.
On the receive side, this SYNC packet will cause multifd channel threads
to block, waiting for the final sem_sync posting in
multifd_r
From: Guenter Roeck
The ClearPortFeature control message fails for PORT_POWER because there
is no break; at the end of the case statement, causing it to fall through
to the failure handler. Add the missing break; to solve the problem.
Fixes: 1cc403eb21 ("usb-hub: emulate per port power switching
From: Richard Henderson
The acc_flag check for write should have been against PAGE_WRITE_ORG,
not PAGE_WRITE. But it is better to combine two acc_flag checks
to a single check against access_type. This matches the system code
in cputlb.c.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com
From: Ilya Leoshkevich
Running qemu-i386 on a system running with SELinux in enforcing mode
(more precisely: s390x trixie container on Fedora 40) fails with:
qemu-i386: tests/tcg/i386-linux-user/sigreturn-sigmask: Unable to find a
guest_base to satisfy all guest address mapping requirements
From: Richard Henderson
Reduce vdso alignment to minimum page size.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
(cherry picked from commit f7150b2151398c9274686d06c2c1e24618aa4cd6)
Signed-off-by: Michael Tokarev
diff --git a/linux-user/arm/Makefile.vdso b/linux-user/
From: Paolo Bonzini
When SET_STREAM_FORMAT is called, the st->buft timer is overwritten, thus
causing a memory leak. This was originally fixed in commit 816139ae6a5
("hw/audio/hda: fix memory leak on audio setup", 2024-11-14) but that
caused the audio to break in SPICE.
Fortunately, a simpler f
From: Helge Deller
The commit fd6f7798ac30 ("linux-user: Use direct syscalls for setuid(),
etc") added direct syscall wrappers for setuid(), setgid(), etc since the
system calls have different semantics than the libc functions.
Add and use the corresponding wrappers for setreuid and setregid whi
From: Peter Maydell
The 'isapc' machine type has no PCI bus, but pc_nic_init() still
calls pci_init_nic_devices() passing it a NULL bus pointer. This
causes the clang sanitizer to complain:
$ ./build/clang/qemu-system-i386 -M isapc
../../hw/pci/pci.c:1866:39: runtime error: member access within
From: Thomas Huth
When compiling QEMU with --enable-cfi, the "q800" m68k machine
currently crashes very early, when the q800_machine_init() function
tries to wire the interrupts of the "via1" device.
This happens because TYPE_MOS6522_Q800_VIA1 is supposed to be a
proper SysBus device, but its par
From: Paolo Bonzini
This reverts commit 6d03242a7e47815ed56687ecd13f683d8da3f2fe,
which causes SPICE audio to break. While arguably this is a SPICE bug,
it is possible to fix the leak in a less heavy-handed way.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2639
Cc: qemu-sta...@nongnu
From: Cédric Le Goater
When commit 96b7af4388b3 intoduced a .instance_finalize() handler,
it did not take into account that the container was not necessarily
inserted into the container list of the address space. Hence, if
the container object is destroyed, by calling object_unref() for
example,
From: Richard Henderson
In be8 mode, instructions are little-endian.
In be32 mode, instructions are big-endian.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2333
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
(cherry picked from commit 95c9e2209cc09453cfd49e913
From: Peter Maydell
In simd_desc() we create a SIMD descriptor from various pieces
including an arbitrary data value from the caller. We try to
sanitize these to make sure everything will fit: the 'data' value
needs to fit in the SIMD_DATA_BITS (== 22) sized field. However we
do that sanitizing
From: Alexander Graf
Commit b56617bbcb4 ("target/i386: Walk NPT in guest real mode") added
logic to run the page table walker even in real mode if we are in NPT
mode. That function then determined whether real mode or paging is
active based on whether the pg_mode variable was 0.
Unfortunately p
From: Pierrick Bouvier
When instrumenting memory accesses for plugin, we force memory accesses
to use the slow path for mmu [1]. This create a situation where we end
up calling ptw_setl_slow. This was fixed recently in [2] but the issue
still could appear out of plugins use case.
Since this func
Hi MST and Marcel,
On 2024/11/19 00:05, Anthony PERARD wrote:
> On Wed, Nov 06, 2024 at 02:14:18PM +0800, Jiqian Chen wrote:
>> In PVH dom0, when passthrough a device to domU, QEMU code
>> xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
>> the gsi number is got from file
18.11.2024 15:39, Philippe Mathieu-Daudé wrote:
On 14/11/24 13:01, Vitaly Kuznetsov wrote:
Commit bbf3810f2c4f ("target/i386: Fix conditional CONFIG_SYNDBG
enablement") broke !CONFIG_SYNDBG builds as hyperv_syndbg_query_options()
is missing there. The idea probably was that as "hv-syndbg" is now
From: Paolo Bonzini
When SET_STREAM_FORMAT is called, the st->buft timer is overwritten, thus
causing a memory leak. This was originally fixed in commit 816139ae6a5
("hw/audio/hda: fix memory leak on audio setup", 2024-11-14) but that
caused the audio to break in SPICE.
Fortunately, a simpler f
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Glenn Miles
>
> When booting with PHYP, the blk/index for a NVGC was being
> mistakenly treated as the blk/index for a NVP. Renamed
> nvp_blk/nvp_idx throughout the code to nvx_blk/nvx_idx to prevent
> confusion in the future and n
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Glenn Miles
>
> END notification processing has an escalation path. The escalation is
> not always an END escalation but can be an ESB escalation.
>
> Also added a check for 'resume' processing which log a message stating it
> need
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB
> value is lower than the new CPPR value, there could be a pending group
> interrupt in the backlog, so it needs to be scanned.
>
> Signed-of
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> When pushing an OS context, we were already checking if there was a
> pending interrupt in the IPB and sending a notification if needed. We
> also need to check if there is a pending group interrupt stored in th
On Thu, Nov 14, 2024 at 7:14 PM Clément Léger wrote:
>
> With the current implementation, if we had the current scenario:
> - set bit x in menvcfg
> - set bit x in henvcfg
> - clear bit x in menvcfg
> then, the internal variable env->henvcfg would still contain bit x due
> to both a wrong menvcfg
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang wrote:
>
> Follow the Svukte spec, do the memory access address checking
>
> 1. Include instruction fetches or explicit memory accesses
> 2. System run in effective privilege U or VU
> 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
> instr
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang wrote:
>
> Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
> value will be masked when the svukte extension is not enabled.
>
> When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
> do svukte check.
>
> Signed-off-by:
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang wrote:
>
> Add "svukte" in the ISA string when svukte extension is enabled.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: Jim Shu
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang wrote:
>
> Add "svukte" in the ISA string when svukte extension is enabled.
>
> Signed-off-by: Fea.Wang
> Reviewed-by: Frank Chang
> Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 i
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang wrote:
>
> Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
> supported when the svukte extension is enabled.
>
> When senvcfg[UKTE] bit is set, the memory access from U-mode should do
> the svukte check only except HLV/HLVX/HSV H-mode
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> If an END has the 'i' bit set (ignore), then it targets a group of
> VPs. The size of the group depends on the VP index of the target
> (first 0 found when looking at the least significant bits of the
> index) so
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang wrote:
>
> Refer to the draft of svukte extension from:
> https://github.com/riscv/riscv-isa-manual/pull/1564
>
> Svukte provides a means to make user-mode accesses to supervisor memory
> raise page faults in constant time, mitigating attacks that attempt t
On Wed, Nov 13, 2024 at 9:06 PM Anton Blanchard wrote:
>
> Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
> 8 wide RV64 cores. More details can be found at
> https://tenstorrent.com/ip/tt-ascalon
>
> Signed-off-by: Anton Blanchard
Acked-by: Alistair Francis
Alistair
>
On Wed, Nov 13, 2024 at 9:06 PM Anton Blanchard wrote:
>
> Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
> 8 wide RV64 cores. More details can be found at
> https://tenstorrent.com/ip/tt-ascalon
>
> Signed-off-by: Anton Blanchard
Thanks!
Applied to riscv-to-apply.next
[This is not for 9.2 release, but for 10.0]
QEMU defines a frequently used helper container_get(), which (from its name
implies) should return a container object of a specific path, normally
starting from object_get_root() (aka, the root of QOM tree, "/"), or some
sub-directory of root.
We mostly
On Mon, 18 Nov 2024 at 20:40, Peter Maydell wrote:
>
> On Mon, 18 Nov 2024 at 02:19, Joel Stanley wrote:
> >
> > Guest code was performing a byte load to the SCU MMIO region, leading to
> > the guest code crashing (it should be using proper accessors, but
> > that is not Qemu's bug). Hardware and
On Wed, Nov 6, 2024 at 11:38 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Now that we have merged the base IOMMU support we can re-introduce
> the riscv-iommu-sys platform device that was taken away from the initial
> posting.
>
> Aside from adding support for the device in the 'virt' machine we'
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Glenn Miles
>
> XIVE crowd sizes are encoded into a 2-bit field as follows:
> 0: 0b00
> 2: 0b01
> 4: 0b10
> 16: 0b11
>
> A crowd size of 8 is not supported.
Squash this into patch 9 as a fix? xive2_pgofnext() is introduced i
On Wed, Nov 6, 2024 at 11:35 PM Daniel Henrique Barboza
wrote:
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> docs/specs/riscv-iommu.rst | 30 +++---
> docs/system/riscv/virt.rst | 10 ++
> 2 files changed, 37 inserti
On Wed, Nov 6, 2024 at 11:35 PM Daniel Henrique Barboza
wrote:
>
> Add a riscv_iommu_reset() helper in the base emulation code that
> implements the expected reset behavior as defined by the riscv-iommu
> spec.
>
> Devices can then use this helper in their own reset callbacks.
>
> Signed-off-by: D
On Wed, Nov 6, 2024 at 11:36 PM Daniel Henrique Barboza
wrote:
>
> From: Sunil V L
>
> Add a new machine option called 'iommu-sys' that enables a
> riscv-iommu-sys platform device for the 'virt' machine. The option is
> default 'off'.
>
> The device will use IRQs 36 to 39.
>
> We will not support
On Mon, 18 Nov 2024 at 10:54, Philippe Mathieu-Daudé wrote:
>
> Hi Iris,
>
> Thanks for this bug report.
>
> On 17/11/24 02:51, Iris Artin wrote:
> > $ brew install qemu
> > Warning: qemu 9.1.1 is already installed and up-to-date.
> > $ qemu-system-avr -version
> > QEMU emulator version 9.1.1
> >
On Wed, Nov 6, 2024 at 11:36 PM Daniel Henrique Barboza
wrote:
>
> MSIx support is added in the RISC-V IOMMU platform device by including
> the required MSIx facilities to alow software to properly setup the MSIx
> subsystem.
>
> We took inspiration of what is being done in the riscv-iommu-pci dev
On Wed, Nov 6, 2024 at 11:38 PM Daniel Henrique Barboza
wrote:
>
> Move all the static initializion of the device to an init() function,
> leaving only the dynamic initialization to be done during realize.
>
> With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
> init(), and rea
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> The NSR has a (so far unused) grouping level field. When a interrupt
> is presented, that field tells the hypervisor or OS if the interrupt
> is for an individual VP or for a VP-group/crowd. This patch reworks
>
On Tue, Oct 29, 2024 at 6:54 PM Yong-Xuan Wang wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> T
Hi Daniel,
Thanks for reporting the problem. I can reproduce this problem with my
local environment, we will investigate this issue ASAP.
Regards
Bibo Mao
On 2024/11/19 上午3:57, Daniel P. Berrangé wrote:
Hi Song / Jason,
We're seeing non-deterministic hangs in our functional test
suite 'test
On Wed, Nov 6, 2024 at 11:39 PM Daniel Henrique Barboza
wrote:
>
> From: Tomasz Jeznach
>
> This device models the RISC-V IOMMU as a sysbus device. The same design
> decisions taken in the riscv-iommu-pci device were kept, namely the
> existence of 4 vectors are available for each interrupt cause
On Wed, Nov 6, 2024 at 11:36 PM Daniel Henrique Barboza
wrote:
>
> Interrupt Generation Support (IGS) is a capability that is tied to the
> interrupt deliver mechanism, not with the core IOMMU emulation. We
> should allow device implementations to set IGS as they wish.
>
> A new helper is added to
On Thu, Nov 14, 2024 at 4:57 PM Jason Chien wrote:
>
> From RISCV IOMMU spec section 2.1.3:
> When SXL is 1, the following rules apply:
> - If the first-stage is not Bare, then a page fault corresponding to the
> original access type occurs if the IOVA has bits beyond bit 31 set to 1.
> - If the s
From: Paolo Bonzini
When SET_STREAM_FORMAT is called, the st->buft timer is overwritten, thus
causing a memory leak. This was originally fixed in commit 816139ae6a5
("hw/audio/hda: fix memory leak on audio setup", 2024-11-14) but that
caused the audio to break in SPICE.
Fortunately, a simpler f
Hello,
I'm currently reviewing the QEMU Arm documentation, and I have a
question about the status of following features:
8.0:
- FEAT_DoubleLock, Double Lock
8.2:
- FEAT_ASMv8p2, Armv8.2 changes to the A64 ISA (bfc and rev64 instructions)
8.4:
- FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse
When used incorrectly, container_get() can silently create containers even
if the caller may not intend to do so. Add a rich document describing the
helper, as container_get() should only be used in path lookups.
Add one object_dynamic_cast() check to make sure whatever objects the
helper walks w
On Mon, Nov 18, 2024 at 05:13:30PM -0500, Peter Xu wrote:
> When used incorrectly, container_get() can silently create containers even
> if the caller may not intend to do so. Add a rich document describing the
> helper, as container_get() should only be used in path lookups.
>
> Add one object_d
Leverage the common code introduced in commit c9cf636d48 ("machine:
Add a valid_cpu_types property") to check for the single valid CPU
type. This allows reporting an error for invalid CPUs:
$ qemu-system-avr -M 2009 -cpu avr51-avr-cpu
qemu-system-avr: Invalid CPU model: avr51
The only valid
On Mon, 2024-11-18 at 10:06 +0100, Cédric Le Goater wrote:
> Add subsubsections for possible boot methods and introduce a new
> section on eMMC boot support for the ast2600-evb and rainier-emmc
> machines, boot partitions assumptions and limitations.
>
> Signed-off-by: Cédric Le Goater
Nice!
Re
Provide a macro for the container type across QEMU source tree, rather than
hard code it every time.
Signed-off-by: Peter Xu
---
include/qom/object.h | 3 ++-
hw/arm/stellaris.c | 2 +-
qom/container.c | 4 ++--
qom/object.c | 4 ++--
4 files changed, 7 insertions(+), 6 deletions(
Currently, a device can be realized even before machine is created, but
only in one of QEMU's qtest, test-global-qdev-props.c.
Right now, the test_static_prop_subprocess() test (which creates one simple
object without machine created) will internally make "/machine" to be a
container, which may no
Currently, qdev_get_machine() has a slightly misuse of container_get(), as
the helper says "get a container" but in reality the goal is to get the
machine object.
Note that it _may_ get a container (at "/machine") in our current unit test
of test-qdev-global-props.c, but it's probably unexpected a
container_get() is going to become strict on not allowing to return a
non-container.
Switch the e500 user to use object_resolve_path_component() explicitly.
Cc: Bharat Bhushan
Cc: qemu-...@nongnu.org
Signed-off-by: Peter Xu
---
hw/pci-host/ppce500.c | 4 ++--
1 file changed, 2 insertions(+), 2
On 11/12/24 13:26, Pierrick Bouvier wrote:
Now that meson build for plugins was merged, we can cleanup another part with
the symbols file.
It has to be kept in sync between the header (qemu-plugin.h) and the symbols
file. This has proved to be error prone and tedious.
We solve this by generating
On 10/23/24 11:29, Pierrick Bouvier wrote:
fixes associated warning when building on MacOS.
Signed-off-by: Pierrick Bouvier
---
target/i386/hvf/x86_task.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
in
From: Helge Deller
The commit fd6f7798ac30 ("linux-user: Use direct syscalls for setuid(),
etc") added direct syscall wrappers for setuid(), setgid(), etc since the
system calls have different semantics than the libc functions.
Add and use the corresponding wrappers for setreuid and setregid whi
On 18/11/2024 16.32, Peter Maydell wrote:
The current 30 minute timeout on the cross_accel_build_job template
is a bit low: sometimes if the k8s runners are running slow the
can hit it, for example this cross-arm64-xen-only job hit the
30 minute timeout while still not quite finished with the com
The following patches are queued for QEMU stable v9.0.4:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.0
Patch freeze is 2024-11-18 (today), and the release is planned for 2024-11-20:
https://wiki.qemu.org/Planning/9.0
Please respond here or CC qemu-sta...@nongnu.org on any addit
From: Peter Maydell
In simd_desc() we create a SIMD descriptor from various pieces
including an arbitrary data value from the caller. We try to
sanitize these to make sure everything will fit: the 'data' value
needs to fit in the SIMD_DATA_BITS (== 22) sized field. However we
do that sanitizing
From: Richard Henderson
In be8 mode, instructions are little-endian.
In be32 mode, instructions are big-endian.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2333
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
(cherry picked from commit 95c9e2209cc09453cfd49e913
From: Guenter Roeck
The ClearPortFeature control message fails for PORT_POWER because there
is no break; at the end of the case statement, causing it to fall through
to the failure handler. Add the missing break; to solve the problem.
Fixes: 1cc403eb21 ("usb-hub: emulate per port power switching
From: Thomas Huth
When compiling QEMU with --enable-cfi, the "q800" m68k machine
currently crashes very early, when the q800_machine_init() function
tries to wire the interrupts of the "via1" device.
This happens because TYPE_MOS6522_Q800_VIA1 is supposed to be a
proper SysBus device, but its par
Junjie Mao writes:
> Alex Bennée writes:
>
>> Junjie Mao writes:
>>
>>> The peripheral and PrimeCell identification registers of pl011 are located
>>> at
>>> offset 0xFE0 - 0xFFC. To check if a read falls to such registers, the C
>>> implementation checks if the offset-shifted-by-2 (not the of
From: Peter Maydell
The 'isapc' machine type has no PCI bus, but pc_nic_init() still
calls pci_init_nic_devices() passing it a NULL bus pointer. This
causes the clang sanitizer to complain:
$ ./build/clang/qemu-system-i386 -M isapc
../../hw/pci/pci.c:1866:39: runtime error: member access within
From: Richard Henderson
Reduce vdso alignment to minimum page size.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
(cherry picked from commit f7150b2151398c9274686d06c2c1e24618aa4cd6)
Signed-off-by: Michael Tokarev
diff --git a/linux-user/arm/Makefile.vdso b/linux-user/
From: Alex Bennée
We were premature if bumping this because some of our builds are still
on older glibs. Just copy the compat handler for now and we can remove
it later.
Fixes: ee293103b0 (plugins: update lockstep to use g_memdup2)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2161
Rev
From: Richard Henderson
This path is reachable with plugins enabled, and provoked
with run-plugin-catch-syscalls-with-libinline.so.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-ID: <20241112141232.321354-1-richard.hender...@linaro.org>
(cherry
From: Pierrick Bouvier
When instrumenting memory accesses for plugin, we force memory accesses
to use the slow path for mmu [1]. This create a situation where we end
up calling ptw_setl_slow. This was fixed recently in [2] but the issue
still could appear out of plugins use case.
Since this func
From: Ilya Leoshkevich
Running qemu-i386 on a system running with SELinux in enforcing mode
(more precisely: s390x trixie container on Fedora 40) fails with:
qemu-i386: tests/tcg/i386-linux-user/sigreturn-sigmask: Unable to find a
guest_base to satisfy all guest address mapping requirements
From: Alexander Graf
Commit b56617bbcb4 ("target/i386: Walk NPT in guest real mode") added
logic to run the page table walker even in real mode if we are in NPT
mode. That function then determined whether real mode or paging is
active based on whether the pg_mode variable was 0.
Unfortunately p
From: Richard Henderson
The acc_flag check for write should have been against PAGE_WRITE_ORG,
not PAGE_WRITE. But it is better to combine two acc_flag checks
to a single check against access_type. This matches the system code
in cputlb.c.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com
From: "Maciej S. Szmigiero"
qemu_loadvm_load_state_buffer() and its load_state_buffer
SaveVMHandler allow providing device state buffer to explicitly
specified device via its idstr and instance id.
Reviewed-by: Fabiano Rosas
Signed-off-by: Maciej S. Szmigiero
---
include/migration/register.h
From: "Maciej S. Szmigiero"
This is an updated v3 patch series of the v2 series located here:
https://lore.kernel.org/qemu-devel/cover.1724701542.git.maciej.szmigi...@oracle.com/
Changes from v2:
* Reworked the non-AIO (generic) thread pool to use Glib's GThreadPool
instead of making the current
From: "Maciej S. Szmigiero"
This property allows configuring at runtime whether to transfer the
particular device state via multifd channels when live migrating that
device.
It defaults to AUTO, which means that VFIO device state transfer via
multifd channels is attempted in configurations that
From: Manos Pitsidianakis
As of Nov 2024 [1], we have a new topical mailing list for Rust
related patches. Add a new MAINTAINERS entry to touch all files under
rust/ subdirectory and additionally add it to previous rust related
entries.
[1]
https://lore.kernel.org/qemu-devel/cafeaca-zquygttg-vh
From: Ilya Leoshkevich
GDB 15 does not like exit() anymore:
(gdb) python exit(0)
Python Exception : 0
Error occurred in Python: 0
Use the GDB's own exit command, like it's already done in a couple
places, everywhere. This is the same fix as commit 93a3048dcf45
("tests: Gently exit f
From: Thomas Huth
When compiling QEMU with --enable-cfi, the "q800" m68k machine
currently crashes very early, when the q800_machine_init() function
tries to wire the interrupts of the "via1" device.
This happens because TYPE_MOS6522_Q800_VIA1 is supposed to be a
proper SysBus device, but its par
On 8/11/24 14:55, Peter Maydell wrote:
Peter Maydell (3):
bitops.h: Define bit operations on 'uint32_t' arrays
hw/intc/arm_gicv3: Use bitops.h uint32_t bit array functions
hw/intc/loongarch_extioi: Use set_bit32() and clear_bit32() for s->isr
Series:
Reviewed-by: Philippe Mathieu-Daud
On 18/11/24 14:32, guoguangyao wrote:
Add alignment and check for fpr in
CPUArchState, fix alignment error in
tcg interpreter when executing LASX.
Signed-off-by: guoguangyao
---
target/loongarch/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Dau
The following changes since commit 0fbc798e4f51d6d2bc05f4965b0eae74ba204471:
Merge tag 'pull-vfio-20241118' of https://github.com/legoater/qemu into
staging (2024-11-18 10:04:04 +)
are available in the Git repository at:
https://gitlab.com/stsquad/qemu.git tags/pull-9.2-
Coverity reports (CID 1564769, 1564770) that we potentially overflow
by doing some 32x32 multiplies for something that ends up in a 64 bit
value. Fix this by first using stride for all lines and casting input
to uint64_t to ensure a 64 bit multiply is used.
Reviewed-by: Dmitry Osipenko
Tested-by:
There are two identical sequences of a code doing the same thing that
raise warnings with Coverity. Before fixing those issues lets factor
out the common code into a helper function we can share.
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
Signed-off-by: Alex Bennée
Message-Id: <202
The following changes since commit abb1565d3d863cf210f18f70c4a42b0f39b8ccdb:
Merge tag 'pull-tcg-20241116' of https://gitlab.com/rth7680/qemu into staging
(2024-11-16 18:16:46 +)
are available in the Git repository at:
https://repo.or.cz/qemu/ericb.git tags/pull-nbd-2024-11-18
for you
From: Richard Henderson
The acc_flag check for write should have been against PAGE_WRITE_ORG,
not PAGE_WRITE. But it is better to combine two acc_flag checks
to a single check against access_type. This matches the system code
in cputlb.c.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com
Hi Song / Jason,
We're seeing non-deterministic hangs in our functional test
suite 'tests/functional/test_loongarch64_virt.py' and my
attempt at git bisect is blaming this commit.
With this applied, perhaps 1 time in 10, the test case hangs,
with zero serial port output from EDK2 emitted
https
On 18.11.24 10:37, Vladimir Sementsov-Ogievskiy wrote:
On 26.10.24 19:30, Vincent Vanlaer wrote:
Signed-off-by: Vincent Vanlaer
---
block/commit.c | 61 --
1 file changed, 34 insertions(+), 27 deletions(-)
diff --git a/block/commit.c b/block/c
Goal
I'd like to know if it is planned for QEMU to be able to emulate the
MPC5553/MPC5554 microcontrollers.
Technical details
-
I know that the e200z6 processor can already be emulated. I don't know how much
work is needed to emulate those microcontrollers fully based on t
On Tue, Nov 5, 2024 at 3:43 AM Sai Pavan Boddu wrote:
>
> Add a basic board with interrupt controller (intc), timer, serial
> (uartlite), small memory called LMB@0 (128kB) and DDR@0x8000
> (configured via command line eg. -m 2g).
> This is basic configuration which matches HW generated out of
1 - 100 of 274 matches
Mail list logo
