On Thu, Nov 14, 2024 at 7:16 PM Clément Léger <cle...@rivosinc.com> wrote: > > Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, > {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the > presence of the Ssdbltrp ISA extension. > > Signed-off-by: Clément Léger <cle...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 6 ++++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/cpu_helper.c | 17 ++++++++++ > target/riscv/csr.c | 70 +++++++++++++++++++++++++++++++++------ > 5 files changed, 85 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 832556cc34..695de5667f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -553,6 +553,7 @@ void riscv_cpu_set_geilen(CPURISCVState *env, > target_ulong geilen); > bool riscv_cpu_vector_enabled(CPURISCVState *env); > void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); > int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); > +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); > G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > MMUAccessType access_type, > int mmu_idx, uintptr_t > retaddr); > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1a5200d1d5..08cc5b2e22 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -558,6 +558,7 @@ > #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ > #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ > #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ > +#define MSTATUS_SDT 0x01000000 > #define MSTATUS_GVA 0x4000000000ULL > #define MSTATUS_MPV 0x8000000000ULL > > @@ -588,6 +589,7 @@ typedef enum { > #define SSTATUS_XS 0x00018000 > #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ > #define SSTATUS_MXR 0x00080000 > +#define SSTATUS_SDT 0x01000000 > > #define SSTATUS64_UXL 0x0000000300000000ULL > > @@ -777,11 +779,13 @@ typedef enum RISCVException { > #define MENVCFG_CBIE (3UL << 4) > #define MENVCFG_CBCFE BIT(6) > #define MENVCFG_CBZE BIT(7) > +#define MENVCFG_DTE (1ULL << 59) > #define MENVCFG_ADUE (1ULL << 61) > #define MENVCFG_PBMTE (1ULL << 62) > #define MENVCFG_STCE (1ULL << 63) > > /* For RV32 */ > +#define MENVCFGH_DTE BIT(27) > #define MENVCFGH_ADUE BIT(29) > #define MENVCFGH_PBMTE BIT(30) > #define MENVCFGH_STCE BIT(31) > @@ -795,11 +799,13 @@ typedef enum RISCVException { > #define HENVCFG_CBIE MENVCFG_CBIE > #define HENVCFG_CBCFE MENVCFG_CBCFE > #define HENVCFG_CBZE MENVCFG_CBZE > +#define HENVCFG_DTE MENVCFG_DTE > #define HENVCFG_ADUE MENVCFG_ADUE > #define HENVCFG_PBMTE MENVCFG_PBMTE > #define HENVCFG_STCE MENVCFG_STCE > > /* For RV32 */ > +#define HENVCFGH_DTE MENVCFGH_DTE > #define HENVCFGH_ADUE MENVCFGH_ADUE > #define HENVCFGH_PBMTE MENVCFGH_PBMTE > #define HENVCFGH_STCE MENVCFGH_STCE > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 092744360e..518102d748 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -77,6 +77,7 @@ struct RISCVCPUConfig { > bool ext_smstateen; > bool ext_sstc; > bool ext_smcntrpmf; > + bool ext_ssdbltrp; > bool ext_svadu; > bool ext_svinval; > bool ext_svnapot; > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 648d4ed833..b9f36e8621 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -63,6 +63,19 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) > #endif > } > > +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) > +{ > +#ifdef CONFIG_USER_ONLY > + return false; > +#else > + if (virt) { > + return (env->henvcfg & HENVCFG_DTE) != 0; > + } else { > + return (env->menvcfg & MENVCFG_DTE) != 0; > + } > +#endif > +} > + > void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, > uint64_t *cs_base, uint32_t *pflags) > { > @@ -562,6 +575,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > > g_assert(riscv_has_ext(env, RVH)); > > + if (riscv_env_smode_dbltrp_enabled(env, current_virt)) { > + mstatus_mask |= MSTATUS_SDT; > + } > + > if (current_virt) { > /* Current V=1 and we are about to change to V=0 */ > env->vsstatus = env->mstatus & mstatus_mask; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 73ac4d5449..054418ff54 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -540,6 +540,15 @@ static RISCVException aia_hmode32(CPURISCVState *env, > int csrno) > return hmode32(env, csrno); > } > > +static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno) > +{ > + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { > + return RISCV_EXCP_NONE; > + } > + > + return hmode(env, csrno); > +} > + > static RISCVException pmp(CPURISCVState *env, int csrno) > { > if (riscv_cpu_cfg(env)->pmp) { > @@ -1600,6 +1609,13 @@ static RISCVException write_mstatus(CPURISCVState > *env, int csrno, > mask |= MSTATUS_VS; > } > > + if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) { > + mask |= MSTATUS_SDT; > + if ((val & MSTATUS_SDT) != 0) { > + val &= ~MSTATUS_SIE; > + } > + } > + > if (xl != MXL_RV32 || env->debugger) { > if (riscv_has_ext(env, RVH)) { > mask |= MSTATUS_MPV | MSTATUS_GVA; > @@ -2356,7 +2372,11 @@ static RISCVException write_menvcfg(CPURISCVState > *env, int csrno, > if (riscv_cpu_mxl(env) == MXL_RV64) { > mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > - (cfg->ext_svadu ? MENVCFG_ADUE : 0); > + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | > + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); > + if ((val & MENVCFG_DTE) == 0) { > + env->mstatus &= ~MSTATUS_SDT; > + } > } > env->menvcfg = (env->menvcfg & ~mask) | (val & mask); > write_henvcfg(env, CSR_HENVCFG, env->henvcfg); > @@ -2379,9 +2399,14 @@ static RISCVException write_menvcfgh(CPURISCVState > *env, int csrno, > const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); > uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > - (cfg->ext_svadu ? MENVCFG_ADUE : 0); > + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | > + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); > uint64_t valh = (uint64_t)val << 32; > > + if ((valh & MENVCFG_DTE) == 0) { > + env->mstatus &= ~MSTATUS_SDT; > + } > + > env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); > write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); > > @@ -2431,9 +2456,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, > int csrno, > * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 > * henvcfg.stce is read_only 0 when menvcfg.stce = 0 > * henvcfg.adue is read_only 0 when menvcfg.adue = 0 > + * henvcfg.dte is read_only 0 when menvcfg.dte = 0 > */ > - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | > - env->menvcfg); > + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | > + HENVCFG_DTE) | env->menvcfg); > return RISCV_EXCP_NONE; > } > > @@ -2457,7 +2483,8 @@ static RISCVException write_henvcfg(CPURISCVState *env, > int csrno, > * keeping stale menvcfg bits in henvcfg value if a bit was enabled > in > * menvcfg and then disabled before updating henvcfg for instance. > */ > - menvcfg_mask = HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE; > + menvcfg_mask = HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | > + HENVCFG_DTE; > mask |= env->menvcfg & menvcfg_mask; > henvcfg_mask |= menvcfg_mask; > } > @@ -2468,6 +2495,9 @@ static RISCVException write_henvcfg(CPURISCVState *env, > int csrno, > * menvcfg enabled bits only. > */ > env->henvcfg = (env->henvcfg & ~henvcfg_mask) | (val & mask); > + if ((env->henvcfg & HENVCFG_DTE) == 0) { > + env->vsstatus &= ~MSTATUS_SDT; > + } > > return RISCV_EXCP_NONE; > } > @@ -2482,8 +2512,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, > int csrno, > return ret; > } > > - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | > - env->menvcfg)) >> 32; > + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | > + HENVCFG_DTE) | env->menvcfg)) >> 32; > return RISCV_EXCP_NONE; > } > > @@ -2495,7 +2525,8 @@ static RISCVException write_henvcfgh(CPURISCVState > *env, int csrno, > * clear all previous menvcfg bits before enabling some new one to avoid > * stale menvcfg bits in henvcfg. > */ > - uint64_t henvcfg_mask = (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); > + uint64_t henvcfg_mask = (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | > + HENVCFG_DTE); > uint64_t mask = env->menvcfg & henvcfg_mask; > uint64_t valh = (uint64_t)val << 32; > RISCVException ret; > @@ -2504,12 +2535,15 @@ static RISCVException write_henvcfgh(CPURISCVState > *env, int csrno, > if (ret != RISCV_EXCP_NONE) { > return ret; > } > - > /* > * 'henvcfg_mask' contains all menvcfg supported bits and 'mask' contains > * menvcfg enabled bits only. > */ > env->henvcfg = (env->henvcfg & ~henvcfg_mask) | (valh & mask); > + if ((env->henvcfg & HENVCFG_DTE) == 0) { > + env->vsstatus &= ~MSTATUS_SDT; > + } > + > return RISCV_EXCP_NONE; > } > > @@ -2937,6 +2971,9 @@ static RISCVException read_sstatus_i128(CPURISCVState > *env, int csrno, > if (env->xl != MXL_RV32 || env->debugger) { > mask |= SSTATUS64_UXL; > } > + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { > + mask |= SSTATUS_SDT; > + } > > *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); > return RISCV_EXCP_NONE; > @@ -2949,6 +2986,9 @@ static RISCVException read_sstatus(CPURISCVState *env, > int csrno, > if (env->xl != MXL_RV32 || env->debugger) { > mask |= SSTATUS64_UXL; > } > + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { > + mask |= SSTATUS_SDT; > + } > /* TODO: Use SXL not MXL. */ > *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); > return RISCV_EXCP_NONE; > @@ -2964,6 +3004,9 @@ static RISCVException write_sstatus(CPURISCVState *env, > int csrno, > mask |= SSTATUS64_UXL; > } > } > + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { > + mask |= SSTATUS_SDT; > + } > target_ulong newval = (env->mstatus & ~mask) | (val & mask); > return write_mstatus(env, CSR_MSTATUS, newval); > } > @@ -4069,6 +4112,13 @@ static RISCVException write_vsstatus(CPURISCVState > *env, int csrno, > if ((val & VSSTATUS64_UXL) == 0) { > mask &= ~VSSTATUS64_UXL; > } > + if ((env->henvcfg & HENVCFG_DTE)) { > + if ((val & SSTATUS_SDT) != 0) { > + val &= ~SSTATUS_SIE; > + } > + } else { > + val &= ~SSTATUS_SDT; > + } > env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; > return RISCV_EXCP_NONE; > } > @@ -5276,7 +5326,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, > .min_priv_ver = PRIV_VERSION_1_12_0 > }, > > - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, > write_mtval2, > + [CSR_MTVAL2] = { "mtval2", dbltrp_hmode, read_mtval2, write_mtval2, > .min_priv_ver = PRIV_VERSION_1_12_0 > }, > [CSR_MTINST] = { "mtinst", hmode, read_mtinst, > write_mtinst, > .min_priv_ver = PRIV_VERSION_1_12_0 > }, > -- > 2.45.2 > >