On Tue, Oct 29, 2024 at 6:54 PM Yong-Xuan Wang <yongxuan.w...@sifive.com> wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The pending bit is cleared whenever the rectified input value is
> low, when the interrupt is forwarded by MSI, or by a relevant
> write to an in_clrip register or to clripnum."
>
> Update the riscv_aplic_set_pending() to match the spec.
>
> Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for
> APLIC MSI-mode")
> Signed-off-by: Yong-Xuan Wang <yongxuan.w...@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v2:
> - add fixes tag (Daniel)
> - follow the suggestion from
> https://lore.kernel.org/kvm/caahsdy3nmwbhy9qef9luexfr0ie7wc-u0d_fhzc47pxk-mz...@mail.gmail.com/
> (Anup)
> ---
> hw/intc/riscv_aplic.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index 4a262c82f078..74c82a841101 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -248,9 +248,12 @@ static void riscv_aplic_set_pending(RISCVAPLICState
> *aplic,
>
> if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
> (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
> - if (!aplic->msimode || (aplic->msimode && !pending)) {
> + if (!aplic->msimode) {
> return;
> }
> + if (aplic->msimode && !pending) {
> + goto noskip_write_pending;
> + }
> if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
> (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
> return;
> @@ -261,6 +264,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState
> *aplic,
> }
> }
>
> +noskip_write_pending:
> riscv_aplic_set_pending_raw(aplic, irq, pending);
> }
>
> --
> 2.17.1
>
>
