On Wed, Nov 6, 2024 at 11:36 PM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> Interrupt Generation Support (IGS) is a capability that is tied to the
> interrupt deliver mechanism, not with the core IOMMU emulation. We
> should allow device implementations to set IGS as they wish.
>
> A new helper is added to make it easier for device impls to set IGS. Use
> it in our existing IOMMU device (riscv-iommu-pci) to set
> RISCV_IOMMU_CAPS_IGS_MSI.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/riscv/riscv-iommu-bits.h | 6 ++++++
> hw/riscv/riscv-iommu-pci.c | 1 +
> hw/riscv/riscv-iommu.c | 5 +++++
> hw/riscv/riscv-iommu.h | 4 ++++
> 4 files changed, 16 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
> index 6359ae0353..485f36b9c9 100644
> --- a/hw/riscv/riscv-iommu-bits.h
> +++ b/hw/riscv/riscv-iommu-bits.h
> @@ -88,6 +88,12 @@ struct riscv_iommu_pq_record {
> #define RISCV_IOMMU_CAP_PD17 BIT_ULL(39)
> #define RISCV_IOMMU_CAP_PD20 BIT_ULL(40)
>
> +enum riscv_iommu_igs_modes {
> + RISCV_IOMMU_CAP_IGS_MSI = 0,
> + RISCV_IOMMU_CAP_IGS_WSI,
> + RISCV_IOMMU_CAP_IGS_BOTH
> +};
> +
> /* 5.4 Features control register (32bits) */
> #define RISCV_IOMMU_REG_FCTL 0x0008
> #define RISCV_IOMMU_FCTL_BE BIT(0)
> diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
> index a42242532d..4ce9bf6b78 100644
> --- a/hw/riscv/riscv-iommu-pci.c
> +++ b/hw/riscv/riscv-iommu-pci.c
> @@ -155,6 +155,7 @@ static void riscv_iommu_pci_init(Object *obj)
> qdev_alias_all_properties(DEVICE(iommu), obj);
>
> iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
> + riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);
> }
>
> static Property riscv_iommu_pci_properties[] = {
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 1893584028..d95b4b95d8 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -2096,6 +2096,11 @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
> }
> };
>
> +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode)
> +{
> + s->cap = set_field(s->cap, RISCV_IOMMU_CAP_IGS, mode);
> +}
> +
> static void riscv_iommu_instance_init(Object *obj)
> {
> RISCVIOMMUState *s = RISCV_IOMMU(obj);
> diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
> index da3f03440c..f9f2827808 100644
> --- a/hw/riscv/riscv-iommu.h
> +++ b/hw/riscv/riscv-iommu.h
> @@ -21,6 +21,9 @@
>
> #include "qom/object.h"
> #include "hw/riscv/iommu.h"
> +#include "hw/riscv/riscv-iommu-bits.h"
> +
> +typedef enum riscv_iommu_igs_modes riscv_iommu_igs_mode;
>
> struct RISCVIOMMUState {
> /*< private >*/
> @@ -85,6 +88,7 @@ struct RISCVIOMMUState {
>
> void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
> Error **errp);
> +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
>
> /* private helpers */
>
> --
> 2.45.2
>
>
