On Mon, Oct 14, 2024 at 7:10 PM Thomas Huth wrote:
>
> The linker on OpenBSD complains:
>
> ld: warning: console-vc.c:824 (../src/ui/console-vc.c:824)([...]):
> warning: sprintf() is often misused, please use snprintf()
>
> Using snprintf() is certainly better here, so let's switch to that
> fun
Philippe Mathieu-Daudé writes:
> On 10/10/24 16:25, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> On 10/10/24 12:01, Markus Armbruster wrote:
The error message for a "stepping" value that is out of bounds is a
bit odd:
$ qemu-system-x86_64 -cpu qemu64,st
Update kernel headers to bring new VirtIO-GPU DRM capset.
Signed-off-by: Dmitry Osipenko
---
include/standard-headers/drm/drm_fourcc.h | 43
include/standard-headers/linux/const.h| 17 ++
include/standard-headers/linux/ethtool.h | 226 ++
include/standard-
Print out error messages when virgl fence creation fails to aid debugging
of the fence-related bugs.
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-v
Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
using a new virtio-gpu-gl device option "drm=on".
Unlike Virgl and Venus contexts that operate on application API level,
DRM native contexts work on a kernel UAPI level. This lower level results
in a lightweight context impl
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
From: Pierre-Eric Pelloux-Prayer
If EGL is used, we can rely on dmabuf to import textures without
doing copies.
To get this working on X11, we use the existing SDL hint:
SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX).
Signed-off-by: Pierre-Eric Pelloux-Prayer
Signed-off-b
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
It's based on the pending Venus v17 patches [1] that bring host blobs
support to virtio-gpu-gl device.
Based-on: 20240822185110.1757429-1-dmitry.osipe...@collabora.com
[1]
https://lore.kernel.org/qemu-devel/20240822185110.17574
SDL API changes GL context to a newly created GL context, which differs
from other GL providers that don't switch context. Change SDL backend to
restore the original GL context. This allows Qemu's virtio-gpu to support
new virglrenderer async-fencing feature for Virgl contexts, otherwise
virglrende
With cpu-add/cpu-del command tested on LoongArch system, no migration
tested. There is no negative influence with LoongArch cpu hotplug.
Regards
Bibo Mao
On 2024/10/15 上午3:22, Salil Mehta via wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after
Under situation where virtual machine is running in a deployment where
the system time is unstable, there is a chance that legacy OpenStack
Windows machines without stimer enabled will crash if system time moves
backwards and diftfix=slew is enabled. This primarily caused by the fact
the system tim
On 2024/10/15 03:34, Stewart Hildebrand wrote:
> +Edgar
>
> On 5/16/24 06:13, Jiqian Chen wrote:
>> In PVH dom0, it uses the linux local interrupt mechanism,
>> when it allocs irq for a gsi, it is dynamic, and follow
>> the principle of applying first, distributing first. And
>> the irq number is
Hi Salil,
On 2024/10/15 上午3:59, Salil Mehta wrote:
Hi Bibo,
From: maobibo
Sent: Monday, October 14, 2024 9:53 AM
To: qemu-devel@nongnu.org; Salil Mehta
Cc: Michael S. Tsirkin ; Peter Maydell
; Salil Mehta ;
zhukeqian ; Jonathan Cameron
; Gavin Shan ;
Vishnu Pajjuri ; Xianglai
On Sat, 2024-10-12 at 08:20 +0200, Cédric Le Goater wrote:
> + Aspeed reviewers. Sorry about that.
All good. Seems sensible in concept and from a cursory glance, so if
you want to tack it on:
Acked-by: Andrew Jeffery
The REX.W prefix is ignored for these instructions.
Mirror the solution already used for INS/OUTS: X86_SIZE_z.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2581
Signed-off-by: Richard Henderson
---
target/i386/tcg/decode-new.c.inc | 8
1 file changed, 4 insertions(+), 4 delet
Sent a v2 to fix a leak issue with tcg_ctx->plugin_tb.
On 10/14/24 15:33, Pierrick Bouvier wrote:
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the last plugin active, we stopped reinitializing
tcg_ctx->plugin_insn, which leads to memory callbacks b
On 10/13/24 11:47, Richard Henderson wrote:
Suggested-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 72240
On 10/14/24 16:22, Philippe Mathieu-Daudé wrote:
MEMOP_IDX() is unused since commit 948f88661c6 ("target/mips:
Use cpu_*_data_ra for msa load/store"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_helper.c | 8
1 file changed, 8 deletions(-)
Reviewed-by:
On 10/9/24 17:50, Pierrick Bouvier wrote:
Eventually fixing the page size > TARGET_PAGE_SIZE performance issues.
E.g. with a 16k or 64k aarch64 guest kernel, we still have TARGET_PAGE_SIZE at
4k, so all
guest pages are "large", and so run into our current behaviour of flushing the
entire tlb
t
MEMOP_IDX() is unused since commit 948f88661c6 ("target/mips:
Use cpu_*_data_ra for msa load/store"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_helper.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_he
On 10/14/24 15:33, Pierrick Bouvier wrote:
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the last plugin active, we stopped reinitializing
tcg_ctx->p
On 10/14/24 15:18, Philippe Mathieu-Daudé wrote:
On 13/10/24 13:05, Richard Henderson wrote:
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
#if !defined(CONFIG_
On 10/14/24 15:01, Paolo Savini wrote:
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data being loaded/stored per iteration amounts to 64 bytes or more.
The optimization consists of calling __builtin_memcpy on chunks of data of 128
bytes between the memory
[[ sorry for the lag $LIFE has been over-full lately ]]
On Thu, Oct 3, 2024 at 3:56 AM Alex Bennée wrote:
> Warner Losh writes:
>
> > On Thu, Oct 3, 2024 at 2:53 AM Warner Losh wrote:
> >
> > On Thu, Sep 26, 2024 at 8:24 AM Alex Bennée
> wrote:
> >
> > One output from this discussion should
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the last plugin active, we stopped reinitializing
tcg_ctx->plugin_insn, which leads to memory callbacks b
On 13/10/24 13:05, Richard Henderson wrote:
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env,
uint32_t df, uint32_t wd,
#if !defined(CONFIG_USER_ONLY)
#define
MEMOP_IDX(DF)
On 13/10/24 15:47, Richard Henderson wrote:
This argument is no longer used.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Philippe Mathie
On 10/10/24 05:36, Paolo Bonzini wrote:
It is used in a couple of places only, both within the same target. Those can
use the cflags just as well, so remove the separate field.
Signed-off-by: Paolo Bonzini
---
include/exec/translator.h | 2 --
accel/tcg/translator.c | 1 -
target/mi
From: Helene CHELIN
This patch improves the performance of the emulation of the RVV unit-stride
loads and stores in the following cases:
- when the data being loaded/stored per iteration amounts to 8 bytes or less.
- when the vector length is 16 bytes (VLEN=128) and there's no grouping of the
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data being loaded/stored per iteration amounts to 64 bytes or more.
The optimization consists of calling __builtin_memcpy on chunks of data of 128
bytes between the memory address of the simulated vector register
This version 3 of the patch adds endianness safety to both the optimizations
brought by the patch set.
It also adds some conditions that allow the __builtin_memcpy to be executed
on chunks of 16 bytes with guarantee of atomicity.
Changes from V2:
- patch 1:
- add condition for the host not to be
If one thread modifies the mappings and another thread prints them,
a situation may occur that the printer thread sees a guest mapping
without a corresponding host mapping, leading to a crash in
open_self_maps_2().
Cc: qemu-sta...@nongnu.org
Fixes: 7b7a3366e142 ("linux-user: Use walk_memory_region
On 14.10.2024 22:31, Richard Henderson wrote:
On 10/14/24 11:02, Michael Tokarev wrote:
On 09.10.2024 03:04, Richard Henderson wrote:
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller
Review
On Mon, 14 Oct 2024 08:25:35 +0100 David Woodhouse wrote:
> On Wed, 2024-10-09 at 17:32 -0700, Jakub Kicinski wrote:
> > On Sun, 06 Oct 2024 08:17:58 +0100 David Woodhouse wrote:
> > > +config PTP_1588_CLOCK_VMCLOCK
> > > + tristate "Virtual machine PTP clock"
> > > + depends on X86_T
Hi Igor,
> From: qemu-devel-bounces+salil.mehta=huawei@nongnu.org devel-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Igor
> Mammedov
> Sent: Monday, October 14, 2024 10:38 AM
>
> On Mon, 14 Oct 2024 16:52:55 +0800
> maobibo wrote:
>
> > Hi Salil,
> >
> > When I debug
+Edgar
On 5/16/24 06:13, Jiqian Chen wrote:
> In PVH dom0, it uses the linux local interrupt mechanism,
> when it allocs irq for a gsi, it is dynamic, and follow
> the principle of applying first, distributing first. And
> the irq number is alloced from small to large, but the
> applying gsi numbe
Hi Bibo,
> From: maobibo
> Sent: Monday, October 14, 2024 9:53 AM
> To: qemu-devel@nongnu.org; Salil Mehta
> Cc: Michael S. Tsirkin ; Peter Maydell
> ; Salil Mehta ;
> zhukeqian ; Jonathan Cameron
> ; Gavin Shan ;
> Vishnu Pajjuri ; Xianglai Li
> ; Miguel Luis ; Shaoqin
> Huang ; Zhao
On 14.10.2024 18:15, Daniel P. Berrangé wrote:
These two lines are the only place in the code that uses the
char response[40];
so even better than switching to snprintf, how about just taking
buffer size out of the picture:
g_autofree *response =
g_strdup_printf("\033[%d;%dR",
On 10/14/24 11:02, Michael Tokarev wrote:
On 09.10.2024 03:04, Richard Henderson wrote:
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: R
The ACPI CPU hotplug states `is_{present, enabled}` must be migrated alongside
other vCPU hotplug states to the destination VM. Therefore, they should be
integrated into the existing CPU Hotplug VM State Description (VMSD) table.
Depending on the architecture and its implementation of CPU hotplug e
Update the `AcpiCpuStatus` for `is_enabled` and `is_present` accordingly when
vCPUs are hot-plugged or hot-unplugged, taking into account the *persistence*
of the vCPUs.
Signed-off-by: Salil Mehta
---
hw/acpi/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/acpi/cpu.c b/hw/acp
Reflect the ACPI CPU hotplug `is_{present, enabled}` states in the `_STA.PRES`
(presence) and `_STA.ENA` (enabled) bits when the guest kernel evaluates the
ACPI `_STA` method during initialization, as well as when vCPUs are hot-plugged
or hot-unplugged. The presence of unplugged vCPUs may need to b
Certain CPU architecture specifications [1][2][3] prohibit changes to CPU
presence after the kernel has booted. This limitation exists because many system
initializations rely on the exact CPU count at boot time and do not expect it to
change later. For example, components like interrupt controller
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after the kernel has booted. This is because many system
initializations depend on the exact CPU count at boot time and do not expect it
to change afterward. For example, components like interrupt controllers
Am 14. Oktober 2024 12:47:52 UTC schrieb Peter Maydell
:
>On Sat, 5 Oct 2024 at 21:57, Bernhard Beschow wrote:
>>
>> A very similar implementation of the same device exists in imx_fec. Prepare
>> for
>> a common implementation by extracting the code into its own files.
>>
>> Signed-off-by: Be
From: Nabih Estefan
Converting error to trace message to avoid spamming of message when
there is nothing to transmit.
Signed-off-by: Nabih Estefan
Signed-off-by: Roque Arcudia Hernandez
---
hw/net/npcm_gmac.c | 5 ++---
hw/net/trace-events | 1 +
2 files changed, 3 insertions(+), 3 deletions
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3195da512..fed64741d1 100644
--- a/target/riscv/cpu.
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 11 ++
target/r
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
From: Tommy Wu
Because the RNMI interrupt trap handler address is implementation defined.
We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
of the harts. It’s very easy for users to set the address based on their
expectation. This patch also adds the functionality to
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741)
* mn
On 09.10.2024 03:04, Richard Henderson wrote:
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Is this a qemu-stable m
Hi Manos,
On 10/14/24 07:48, Manos Pitsidianakis wrote:
Add system test to make sure FEAT_XS is enabled for max cpu emulation
and that QEMU doesn't crash when encountering an NXS instruction
variant.
Signed-off-by: Manos Pitsidianakis
---
tests/tcg/aarch64/system/feat-xs.c | 27 +
Hi Manos,
On 10/14/24 07:48, Manos Pitsidianakis wrote:
This series is an initial incomplete attempt at adding support for the
FEAT_XS feature in aarch64 TCG. This feature was introduced in ARMv8.7:
it adds a new memory attribute XS which indicates that a memory access
could take longer than usu
On Mon, 14 Oct 2024, Peter Maydell wrote:
On Sun, 6 Oct 2024 at 17:50, BALATON Zoltan wrote:
Currently -d guest_errors enables logging of different invalid actions
by the guest such as misusing hardware, accessing missing features or
invalid memory areas. The memory access logging can be quite
On Mon, 14 Oct 2024, Peter Maydell wrote:
On Sun, 6 Oct 2024 at 17:49, BALATON Zoltan wrote:
Rename guest_errors to guest_error to match the log constant
I don't think this is a good reason to change the user-facing
behaviour. Also, I don't think the existing names are so bad:
-d guest_erro
On Mon, 14 Oct 2024 at 11:50, Manos Pitsidianakis
wrote:
>
> This series is an initial incomplete attempt at adding support for the
> FEAT_XS feature in aarch64 TCG. This feature was introduced in ARMv8.7:
> it adds a new memory attribute XS which indicates that a memory access
> could take longer
On 10/14/24 03:48, Manos Pitsidianakis wrote:
Add system test to make sure FEAT_XS is enabled for max cpu emulation
and that QEMU doesn't crash when encountering an NXS instruction
variant.
Signed-off-by: Manos Pitsidianakis
---
tests/tcg/aarch64/system/feat-xs.c | 27 +
On 10/14/24 03:48, Manos Pitsidianakis wrote:
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
Signed-off-by: Manos Pitsidianakis
---
target/arm/tcg/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index
0168
On 10/14/24 03:48, Manos Pitsidianakis wrote:
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
Signed-off-by: Manos Pitsidianakis
---
target/arm/tcg/cpu64.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 10/14/24 03:48, Manos Pitsidianakis wrote:
+static bool trans_DSB_nXS(DisasContext *ctx, arg_DSB_nXS *a)
+{
+tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
+return true;
+}
This is missing the feature test:
if (!dc_isar_feature(aa64_xs, ctx)) {
return false;
}
r~
On 10/11/24 10:52 PM, Shivaprasad G Bhat wrote:
On 9/18/24 7:57 PM, Cédric Le Goater wrote:
Hello,
Adding :
Harsh for QEMU/PPC pseries machine,
Shivaprasad for KVM/PPC VFIO and IOMMU support.
Could you please give us your feedback on these changes ?
Thanks,
C.
On 9/13/24 05:44, A
On Mon, 14 Oct 2024 at 12:01, Paolo Bonzini wrote:
>
> If the defaults for --enable-rust ($rust in configure) and Meson's rust
> option are out of sync, incremental builds will pick Meson's default.
>
> This happens because, on an incremental build, configure does not run
> Meson, Make does instea
On 10/14/24 03:48, Manos Pitsidianakis wrote:
Signed-off-by: Manos Pitsidianakis
---
target/arm/cpu-features.h | 5 +
target/arm/helper.c | 366 +++---
2 files changed, 218 insertions(+), 153 deletions(-)
diff --git a/target/arm/cpu-features.h
On 10/12/24 5:40 PM, Akihiko Odaki wrote:
On 2024/10/12 2:22, Shivaprasad G Bhat wrote:
On 9/18/24 7:57 PM, Cédric Le Goater wrote:
Adding :
Harsh for QEMU/PPC pseries machine,
Shivaprasad for KVM/PPC VFIO and IOMMU support.
Thanks,
C.
On 9/13/24 05:44, Akihiko Odaki wrote:
A PF may
On 10/14/24 6:04 AM, Frank Chang wrote:
Clément Léger 於 2024年10月14日 週一 下午3:36寫道：
On 11/10/2024 13:38, Daniel Henrique Barboza wrote:
Hi Tommy,
Do you plan to send a new version of this work soon? This series is a
prerequisite
of "target/riscv: Add support for Smdbltrp and Ssdbltrp exte
On Mon, 14 Oct 2024 at 14:03, Daniel P. Berrangé wrote:
>
> This addresses the py311-yaml -> py311-pyyaml rename in FreeBSD.
>
> The change to the OpenSUSE dockerfile is something that will allow
> QEMU to access rust bindgen in future.
>
> Signed-off-by: Daniel P. Berrangé
> ---
Applied directl
On Mon, 14 Oct 2024 at 15:36, Paolo Bonzini wrote:
>
> A working native Rust compiler is always needed in order to compile Rust
> code, even when cross compiling, in order to build the procedural macros
> that QEMU uses.
>
> Right now, the check is done in rust/qemu-api-macros/meson.build, but thi
Hi,
A couple of weeks ago I posted a patch to GDB adding support to the
Linux backend for user space threads such as qemu's coroutines:
https://sourceware.org/pipermail/gdb-patches/2024-September/212028.html
Within the patch is an example of how to maintain data structures within
userspace for
There is no sense to keep `focus`, `mux_cnt`, `prod`, `cons`
and `tag` variables as signed, those represent either size,
either position in array, which both are unsigned.
`focus` member of `MuxChardev` is kept signed, because initially
set to -1.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lur
With bitset management now it becomes feasible to implement
the logic of detaching frontends from multiplexer.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/char-fe.c | 2 +-
chardev/char-mux.c | 21 ++---
chardev/ch
Frontends can be attached and detached during run-time (although detach
is not implemented, but will follow). Counter variable of muxes is not
enough for proper attach/detach management, so this patch implements
bitset: if bit is set for the `mux_bitset` variable, then frontend
device can be found
`mux_cnt` struct member never goes negative or decrements,
so mux chardev can be !busy only when there are no
frontends attached. This patch fixes the always-true
check.
Fixes: a4afa548fc6d ("char: move front end handlers in CharBackend")
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc:
This patch tests:
1. feasibility of removing mux which does not have frontends attached
or frontends were prior detached.
2. inability to remove mux which has frontends attached (mux is "busy")
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
tests/unit/tes
Clean up forgotten leftovers.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/chardev-internal.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/chardev/chardev-internal.h b/chardev/chardev-internal.h
index 4e03af31476c..c3024b51fdda 100644
--- a/ch
Frontend device can be detached in run-time, which can lead to a
"Chardev 'MUX' is busy" error (see the last patch with the test case
implementation). This series implements frontend detach for the
multiplexer based on bitset, which provides the ability to attach or
detach frontend devices in any o
Move away logic which attaches frontend device to a mux
from `char-fe.c` to actual `char-mux.c` implementation
and make it a separate function.
No logic changes are made.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/char-fe.c | 9 +---
Those are boolean variables, not signed integers.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/char-mux.c | 10 +-
chardev/chardev-internal.h | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/chardev/char-mux.
On Mon, 7 Oct 2024 at 12:25, Chao Liu wrote:
>
> Hi, maintainer,
>
> Following the reference from the chip manualug585-Zynq-7000-TRM manual
> B.3 (Module Summary), placeholders have been added for all unimplemented
> devices, including the AXI and AMBA bus controllers that interact with
> the FPGA
On Mon, 7 Oct 2024 at 12:25, Chao Liu wrote:
>
> Add xilinx zynq board memory mapping is implemented in the device.
>
> Remove a ignore_memory_transaction_failures concurrently.
>
> See: ug585-Zynq-7000-TRM manual B.3 (Module Summary)
> Signed-off-by: Chao Liu
The list of new unimplemented devic
On 14/10/2024 10:30, Laurent Vivier wrote:
Hi Akihiko,
On 04/06/2024 09:37, Jason Wang wrote:
From: Akihiko Odaki
Multiqueue usage is not negotiated yet when realizing. If more than
one queue is added and the guest never requests to enable multiqueue,
the extra queues will not be deleted when
On Mon, Oct 14, 2024 at 05:10:23PM +0200, Thomas Huth wrote:
> The linker on OpenBSD complains:
>
> ld: warning: console-vc.c:824 (../src/ui/console-vc.c:824)([...]):
> warning: sprintf() is often misused, please use snprintf()
>
> Using snprintf() is certainly better here, so let's switch to t
On Mon, 7 Oct 2024 at 12:25, Chao Liu wrote:
>
> During the initialization phase, we've encountered an issue where the
> UNLOCK register is inadvertently cleared. This results in devcfg MR being
> disabled, which in turn leads to unexpected memory access exceptions when
> attempting subsequent acc
On Mon, 7 Oct 2024 at 12:25, Chao Liu wrote:
>
> Signed-off-by: Chao Liu
> ---
> hw/dma/xlnx-zynq-devcfg.c | 2 +-
> include/hw/dma/xlnx-zynq-devcfg.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
> index
The linker on OpenBSD complains:
ld: warning: console-vc.c:824 (../src/ui/console-vc.c:824)([...]):
warning: sprintf() is often misused, please use snprintf()
Using snprintf() is certainly better here, so let's switch to that
function instead.
Signed-off-by: Thomas Huth
---
ui/console-vc.c |
On Mon, Oct 14, 2024 at 11:22:21AM -0300, Fabiano Rosas wrote:
> Daniel P. Berrangé writes:
>
> > On Fri, Oct 11, 2024 at 11:34:17AM -0400, Peter Xu wrote:
> >> This reverts two commits:
> >>
> >> 671326201dac8fe91222ba0045709f04a8ec3af4
> >> 1b1f4ab69c41279a45ccd0d3178e83471e6e4ec1
> >>
> >> M
On Mon, Oct 14, 2024 at 4:41 PM Peter Maydell wrote:
>
> On Mon, 14 Oct 2024 at 15:38, Peter Maydell wrote:
> >
> > On Mon, 14 Oct 2024 at 15:36, Paolo Bonzini wrote:
> > >
> > > A working native Rust compiler is always needed in order to compile Rust
> > > code, even when cross compiling, in or
On Mon, 14 Oct 2024 at 15:38, Peter Maydell wrote:
>
> On Mon, 14 Oct 2024 at 15:36, Paolo Bonzini wrote:
> >
> > A working native Rust compiler is always needed in order to compile Rust
> > code, even when cross compiling, in order to build the procedural macros
> > that QEMU uses.
> >
> > Right
On Mon, 14 Oct 2024 at 15:36, Paolo Bonzini wrote:
>
> A working native Rust compiler is always needed in order to compile Rust
> code, even when cross compiling, in order to build the procedural macros
> that QEMU uses.
>
> Right now, the check is done in rust/qemu-api-macros/meson.build, but thi
A working native Rust compiler is always needed in order to compile Rust
code, even when cross compiling, in order to build the procedural macros
that QEMU uses.
Right now, the check is done in rust/qemu-api-macros/meson.build, but this
has two disadvantages. First, it makes the build fail when t
Daniel P. Berrangé writes:
> On Fri, Oct 11, 2024 at 11:34:17AM -0400, Peter Xu wrote:
>> This reverts two commits:
>>
>> 671326201dac8fe91222ba0045709f04a8ec3af4
>> 1b1f4ab69c41279a45ccd0d3178e83471e6e4ec1
>>
>> Meanwhile it adds an entry to removed-features.rst for the
>> query-migrationthrea
On Sat, 12 Oct 2024 at 07:50, Akihiko Odaki wrote:
>
> Ensure the function names match.
>
> Signed-off-by: Akihiko Odaki
Applied to target-arm.next, thanks.
-- PMM
On Mon, Oct 14, 2024 at 12:21 PM Thomas Huth wrote:
> On 14/10/2024 11.06, Peter Maydell wrote:
> > On Mon, 14 Oct 2024 at 02:13, Andrew Randrianasulu
> > wrote:
> >>
> >> some 8 years ago this patch was sent to qemu-devel:
> >>
> >> https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg0533
On Sun, 6 Oct 2024 at 17:49, BALATON Zoltan wrote:
>
> Rename guest_errors to guest_error to match the log constant
I don't think this is a good reason to change the user-facing
behaviour. Also, I don't think the existing names are so bad:
-d guest_errors
this is plural because we are asking
On Sun, 6 Oct 2024 at 17:50, BALATON Zoltan wrote:
>
> Currently -d guest_errors enables logging of different invalid actions
> by the guest such as misusing hardware, accessing missing features or
> invalid memory areas. The memory access logging can be quite verbose
> which obscures the other me
On Mon, Oct 14, 2024 at 3:57 PM Marc-André Lureau
wrote:
>
> Hi Roman,
>
> On Thu, Oct 10, 2024 at 2:21 PM Roman Penyaev wrote:
>>
>> In the following patches backend multiplexer will be
>> introduced and the implementation will be named as
>> follows: `char-mux-be.c`. This patch renames the
>> f
On Mon, Oct 14, 2024 at 5:58 PM Roman Penyaev wrote:
> On Mon, Oct 14, 2024 at 3:20 PM Marc-André Lureau
> wrote:
> >
> >
> >
> > On Mon, Oct 14, 2024 at 3:45 PM Roman Penyaev
> wrote:
> >>
> >> Frontends can be attached and detached during run-time (although detach
> >> is not implemented, but
On Mon, Oct 14, 2024 at 3:22 PM Marc-André Lureau
wrote:
[cut]
>>
>> +bool mux_chr_detach_frontend(MuxChardev *d, unsigned int tag)
>> +{
>> +unsigned int bit;
>> +
>> +bit = find_next_bit(&d->mux_bitset, MAX_MUX, tag);
>> +if (bit >= MAX_MUX) {
>
>
> if (bit != tag) instead?
Right,
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