[PULL 49/61] target/riscv: Create current pm fields in env

2022-01-20 Thread Alistair Francis
From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20220120122050.41546-12-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 4 target/riscv/cpu.c| 1 + target/riscv/cpu_helper.

[PULL 59/61] target/riscv: Set default XLEN for hypervisor

2022-01-20 Thread Alistair Francis
From: LIU Zhiwei When swap regs for hypervisor, the value of vsstatus or mstatus_hs should have the right XLEN. Otherwise, it will propagate to mstatus. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-22-zhiwei_...@c-sky.com Signed-off-by: Alistair Fran

[PULL 38/61] roms/opensbi: Remove ELF images

2022-01-20 Thread Alistair Francis
From: Anup Patel Now that all RISC-V machines can use OpenSBI BIN images, we remove OpenSBI ELF images and also exclude these images from BIOS build. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Alistair Francis --- .gitlab-ci.d/opensbi.yml

[PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns

2022-01-20 Thread Alistair Francis
From: Frank Chang Zve32f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Mes

[PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns

2022-01-20 Thread Alistair Francis
From: Frank Chang All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-13-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 fil

[PULL 52/61] target/riscv: Split pm_enabled into mask and base

2022-01-20 Thread Alistair Francis
From: LIU Zhiwei Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220120122050.4154

[PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN

2022-01-20 Thread Alistair Francis
From: LIU Zhiwei When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-21-zhiwe

[PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns

2022-01-20 Thread Alistair Francis
From: Frank Chang Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-10-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/

[PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns

2022-01-20 Thread Alistair Francis
From: Frank Chang Vector widening conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-9-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/ri

[PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

2022-01-20 Thread Alistair Francis
From: Frank Chang Vector single-width floating-point reduction operations for EEW=32 are supported for Zve64f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-8-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_tr

[PULL 47/61] target/riscv: Relax debug check for pm write

2022-01-20 Thread Alistair Francis
From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-10-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/

[PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns

2022-01-20 Thread Alistair Francis
From: Frank Chang All Zve* extensions support all vector fixed-point arithmetic instructions, except that vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-6-frank.ch...@sifive.com Signed-off-

[PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

2022-01-20 Thread Alistair Francis
From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-12-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/cpu.c| 4 ++-- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c

[PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns

2022-01-20 Thread Alistair Francis
From: Frank Chang All Zve* extensions support all vector integer instructions, except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*. Signed-off-by: Frank C

[PULL 51/61] target/riscv: Calculate address according to XLEN

2022-01-20 Thread Alistair Francis
From: LIU Zhiwei Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-14-zhiwei_...@c-sky.c

[PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns

2022-01-20 Thread Alistair Francis
From: Frank Chang Zve64f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Mes

[PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

2022-01-20 Thread Alistair Francis
From: Frank Chang Vector single-width floating-point reduction operations for EEW=32 are supported for Zve32f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-15-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_t

[PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V

2022-01-20 Thread Alistair Francis
From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-2-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/cpu.c| 4 target/riscv/cpu_helper.c | 5 - target/riscv/csr.c

[PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang Si

[PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns

2022-01-20 Thread Alistair Francis
From: Frank Chang All Zve* extensions support all vector load and store instructions, except Zve64* extensions do not support EEW=64 for index values when XLEN=32. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-4-frank.ch...@sifive.com Signed-off-by:

[PULL 10/61] target/riscv: Support setting external interrupt by KVM

2022-01-20 Thread Alistair Francis
From: Yifei Jiang When KVM is enabled, set the S-mode external interrupt through kvm_riscv_set_irq function. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-8-jiangyi...@huawei.com Signed-off-by: Alis

[PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on

2022-01-20 Thread Alistair Francis
From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-11-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cdb893

[PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns

2022-01-20 Thread Alistair Francis
From: Frank Chang All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-3-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 fi

[PULL 16/61] target/riscv: enable riscv kvm accel

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Add riscv kvm support in meson.build file. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-14-jiangyi...@huawei.com Signed-off-by: Alistair Francis --- meson.build | 2 ++ 1 file c

[PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Use char-fe to handle console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20220112081329.1835-9-jiangyi.

[PULL 08/61] target/riscv: Implement kvm_arch_put_registers

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-6-jiangyi...@huawei.com Signed-off-by: Alistair Francis --- target/risc

[PULL 15/61] target/riscv: Support virtual time context synchronization

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Add virtual time context description to vmstate_kvmtimer. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20220112081329.1835-13-jiangyi..

[PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment

2022-01-20 Thread Alistair Francis
From: Yanan Wang The pointer assignment "const char *p = path;" in function qemu_fdt_add_path is unnecessary. Let's remove it and just use the "path" passed in. No functional change. Suggested-by: Richard Henderson Signed-off-by: Yanan Wang Reviewed-by: Andrew Jones Reviewed-by: Alistair Fran

[PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Add asm-riscv/kvm.h for RISC-V KVM. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Acked-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-2-jiangyi...@huawei.com Signed-off-by: Alistair Francis --- linux-headers/asm-riscv/kvm.h | 128 +++

[PULL 12/61] target/riscv: Add host cpu type

2022-01-20 Thread Alistair Francis
From: Yifei Jiang 'host' type cpu is set isa to RV32 or RV64 simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-10-jiangyi...@huawei.com

[PULL 07/61] target/riscv: Implement kvm_arch_get_registers

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-5-jiangyi...@huawei.com Signed-off-by: Alistair Francis --- target/r

[PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing

2022-01-20 Thread Alistair Francis
From: Yifei Jiang We hope that virtual time adjusts with vm state changing. When a vm is stopped, guest virtual time should stop counting and kvm_timer should be stopped. When the vm is resumed, guest virtual time should continue to count and kvm_timer should be restored. Signed-off-by: Yifei Ji

[PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-4-jiangyi...@huawei.com Signed-off-by: Alistair Francis --- target/riscv/kvm.c | 34 ++

[PULL 02/61] riscv: opentitan: fixup plic stride len

2022-01-20 Thread Alistair Francis
From: Wilfred Mallawa The following change was made to rectify incorrectly set stride length on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was discovered whilst attempting to fix a bug where a timer_interrupt was not serviced on TockOS-OpenTitan. [1] https://docs.opentitan

[PULL 09/61] target/riscv: Support start kernel directly by KVM

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. Add kvm_riscv.h to place riscv specific interface. In addition, PLIC is created without M-mode PLIC contexts when KVM is enabled. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-b

[PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

2022-01-20 Thread Alistair Francis
From: Yifei Jiang Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-id: 20220112081329.1835-3-jiangyi...@huawei.com Signed-off-by: Alistair Francis

[PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers

2022-01-20 Thread Alistair Francis
From: Thomas Huth If I configure my build with --enable-sanitizers, my GCC (v8.5.0) complains: .../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’: .../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized in this function [-Werror=maybe-uninitialized] int namelen,

[PULL 03/61] hw: timer: ibex_timer: update/add reg address

2022-01-20 Thread Alistair Francis
From: Wilfred Mallawa The following changes: 1. Fixes the incorrectly set CTRL register address. As per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table The CTRL register is @ 0x04. This was found when attempting to fixup a bug where a timer_interrupt was not serviced on TockOS

[PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register

2022-01-20 Thread Alistair Francis
From: Wilfred Mallawa This change fixes a bug where a write only register is read. As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table the 'INTR_TEST0' register is write only. Signed-off-by: Wilfred Mallawa Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Phil

[PULL 00/61] riscv-to-apply queue

2022-01-20 Thread Alistair Francis
From: Alistair Francis The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20 16:13:17 +) are available in the Git repository at: g...@github.com:

[PATCH v1] include: hw: remove ibex_plic.h

2022-01-20 Thread Alistair Francis
From: Wilfred Mallawa This patch removes the left-over/unused `ibex_plic.h` file. Previously used by opentitan, which now follows the RISC-V standard and uses the SiFivePlicState. Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC") Signed-off-by: Wilfred Mallawa --- include/hw/intc/ibex_plic.h

Re: [PATCH] hw/armv7m: Fix broken VMStateDescription

2022-01-20 Thread Ani Sinha
On Thu, 20 Jan 2022, Peter Maydell wrote: > In commit d5093d961585f02 we added a VMStateDescription to > the TYPE_ARMV7M object, to handle migration of its Clocks. > However a cut-and-paste error meant we used the wrong struct > name in the VMSTATE_CLOCK() macro arguments. The result was > that

Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension

2022-01-20 Thread Alistair Francis
On Fri, Jan 21, 2022 at 1:38 AM Philipp Tomsich wrote: > > Thanks for taking the time to write this up! > > On Wed, 19 Jan 2022 at 02:30, Alistair Francis wrote: > > > > On Wed, Jan 19, 2022 at 11:19 AM Alistair Francis > > wrote: > > > > > > On Wed, Jan 19, 2022 at 9:22 AM Philipp Tomsich > >

[PATCH 3/3] crypto: Introduce RSA algorithm

2022-01-20 Thread zhenwei pi
From: Lei He Implement RSA algorithm by nettle hogweed, and apply it for virtio-crypto akcipher backend. 1, The self-test framework of crypto layer works fine in guest kernel 2, Test with Linux guest(with asym support), the following script test(note that pkey_XXX is supported only in a newer ve

[PATCH 2/3] virtio_crypto: Support virtio crypto asym operation

2022-01-20 Thread zhenwei pi
Several changes in this patch: - Add support for virtio crypto asymmetric handling, include: create/close session encrypt/decrypt/sign/verify guest data - Modify crypto backend to compat sym&asym operation. - Introduce akcipher class without any implementation. Then QEMU can provide

[PATCH 0/3] Support akcipher for virtio-crypto

2022-01-20 Thread zhenwei pi
- Support akcipher for virtio-crypto. - Introduce akcipher class. - Introduce ASN1 decoder into QEMU. - Implement RSA backend by nettle/hogweed. Lei He (1): crypto: Introduce RSA algorithm Zhenwei Pi (2): virtio-crypto: header update virtio_crypto: Support virtio crypto asym operation bac

[PATCH 1/3] virtio-crypto: header update

2022-01-20 Thread zhenwei pi
Update header from linux, support akcipher service. Signed-off-by: lei he Signed-off-by: zhenwei pi --- .../standard-headers/linux/virtio_crypto.h| 98 +-- 1 file changed, 89 insertions(+), 9 deletions(-) diff --git a/include/standard-headers/linux/virtio_crypto.h b/includ

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

2022-01-20 Thread LIU Zhiwei
On 2022/1/21 上午9:50, Guo Ren wrote: On Fri, Jan 21, 2022 at 6:48 AM LIU Zhiwei wrote: On 2022/1/20 下午9:47, Guo Ren wrote: Hi Alistair and Anup, On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis wrote: On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote: On Tue, Jan 18, 2022 at 6:47 AM Wei

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

2022-01-20 Thread Guo Ren
On Fri, Jan 21, 2022 at 6:48 AM LIU Zhiwei wrote: > > > On 2022/1/20 下午9:47, Guo Ren wrote: > > Hi Alistair and Anup, > > > > On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis > > wrote: > >> On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote: > >>> On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrot

[PATCH] python: pin setuptools below v60.0.0

2022-01-20 Thread John Snow
setuptools is a package that replaces the python stdlib 'distutils'. It is generally installed by all venv-creating tools "by default". It isn't actually needed at runtime for the qemu package, so our own setup.cfg does not mention it as a dependency. However, tox will create virtual environments

Re: [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties

2022-01-20 Thread Alistair Francis
On Wed, Jan 19, 2022 at 11:09 PM Weiwei Li wrote: > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > i

Re: [RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension

2022-01-20 Thread Alistair Francis
On Wed, Jan 19, 2022 at 9:52 PM Weiwei Li wrote: > > - reuse partial instructions of zbb extension, update extension check for > them > - add brev8, pack, packh, packw, unzip, zip instructions > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Alistair

Re: [RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension

2022-01-20 Thread Alistair Francis
On Wed, Jan 19, 2022 at 9:39 PM Weiwei Li wrote: > > - reuse partial instructions of zbc extension, update extension check for > them > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn32.decode | 3 ++-

Re: [PATCH v8 00/23] Support UXL filed in xstatus

2022-01-20 Thread Alistair Francis
On Fri, Jan 21, 2022 at 1:51 AM LIU Zhiwei wrote: > > In this patch set, we process the pc reigsters writes, > gdb reads and writes, and address calculation under > different UXLEN settings. > > The patch set v8 has been tested by running rv64 Linux with > rv32 rootfs in compat mode. You can almos

Re: [PATCH 1/1] Allow setting up to 8 bytes with the generic loader

2022-01-20 Thread Alistair Francis
On Thu, Jan 20, 2022 at 7:57 PM Petr Tesarik wrote: > > The documentation for the generic loader says that "the maximum size of > the data is 8 bytes". However, attempts to set data-len=8 trigger the > following assertion failure: > > ../hw/core/generic-loader.c:59: generic_loader_reset: Assertion

Re: [PATCH] target/ppc: 603: fix restore of GPRs 0-3 on rfi

2022-01-20 Thread Cédric Le Goater
On 1/20/22 11:39, Christophe Leroy wrote: After a TLB miss exception, GPRs 0-3 must be restored on rfi. This is managed by hreg_store_msr() which is called by do_rfi() However, hreg_store_msr() does it if MSR[TGPR] is unset in the passed MSR value. The problem is that do_rfi() is given the con

Re: [PATCH v2 2/5] python: use avocado's "new" runner

2022-01-20 Thread John Snow
On Thu, Jan 20, 2022 at 8:08 AM Beraldo Leal wrote: > > On Wed, Jan 19, 2022 at 02:39:13PM -0500, John Snow wrote: > > The old legacy runner no longer seems to work with output logging, so we > > can't see failure logs when a test case fails. The new runner doesn't > > (seem to) support Coverage.p

Re: [PATCH 1/2] python: introduce qmp-shell-wrap convenience tool

2022-01-20 Thread John Snow
On Thu, Jan 20, 2022 at 8:40 AM Daniel P. Berrangé wrote: > > On Thu, Jan 20, 2022 at 02:33:46PM +0100, Philippe Mathieu-Daudé wrote: > > On 18/1/22 19:04, John Snow wrote: > > > On Tue, Jan 18, 2022 at 5:06 AM Daniel P. Berrangé > > > wrote: > > > > > > It would be nice to just have this integr

Re: [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup

2022-01-20 Thread Cédric Le Goater
On 1/18/22 19:44, Fabiano Rosas wrote: The 405 ISI does not set SRR1 with any exception syndrome bits, only a clean copy of the MSR. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.

Re: [PATCH v3 0/3] Improve RISC-V spike machine bios support

2022-01-20 Thread Alistair Francis
On Fri, Jan 21, 2022 at 1:49 AM Anup Patel wrote: > > This series aims at improving RISC-V spike machine BIOS support by allowing > use of binary firmware as bios. Further, this also allows us to totally > remove the ELF bios images shipped with QEMU RISC-V. > > These patches can also be found in

Re: [PATCH v3 00/31] Python: delete synchronous qemu.qmp package

2022-01-20 Thread John Snow
On Mon, Jan 10, 2022 at 6:29 PM John Snow wrote: > > Based-on: <20220110232521.1922962-1-js...@redhat.com> > (jsnow/python staging branch) > GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-qmp-legacy-switch > CI: https://gitlab.com/jsnow/qemu/-/pipelines/445163212 > > Hi, this ser

Re: [PATCH] hw/nvme: fix CVE-2021-3929

2022-01-20 Thread Klaus Jensen
On Jan 20 07:10, Keith Busch wrote: > On Thu, Jan 20, 2022 at 09:01:55AM +0100, Klaus Jensen wrote: > > +static inline bool nvme_addr_is_iomem(NvmeCtrl *n, hwaddr addr) > > +{ > > +hwaddr hi, lo; > > + > > +lo = n->bar0.addr; > > +hi = lo + int128_get64(n->bar0.size); > > + > > +ret

Re: [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

2022-01-20 Thread Alistair Francis
On Thu, Jan 20, 2022 at 1:41 AM Anup Patel wrote: > > From: Anup Patel > > The AIA specification introduces new [m|s|vs]topi CSRs for > reporting pending local IRQ number and associated IRQ priority. > > Signed-off-by: Anup Patel > Signed-off-by: Anup Patel > Reviewed-by: Frank Chang Acked-by

[RFC 1/5] target/riscv: Add the privileged spec version 1.12.0

2022-01-20 Thread Atish Patra
Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d630867650a..671f65100b1a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv

[RFC 0/5] Privilege version update

2022-01-20 Thread Atish Patra
RISC-V International (RVI) has ratified many RISC-V ISA extensions recently[1]. The privileged specification version is also upgraded to v1.12. It means certain CSRs introduced in v1.12 should only be accessible only if the priv specification version supported is equal or greater than v1.12. Doing

Re: [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

2022-01-20 Thread Alistair Francis
On Thu, Jan 20, 2022 at 2:32 AM Anup Patel wrote: > > From: Anup Patel > > The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs > which allow indirect access to interrupt priority arrays and per-HART > IMSIC registers. This patch implements AIA xiselect and xireg CSRs. > > Signed-o

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

2022-01-20 Thread LIU Zhiwei
On 2022/1/20 下午9:47, Guo Ren wrote: Hi Alistair and Anup, On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis wrote: On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2

[RFC 5/5] target/riscv: Enable privileged spec version 1.12

2022-01-20 Thread Atish Patra
Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 10 ++ 2 files chan

[RFC 3/5] target/riscv: Add support for mconfigptr

2022-01-20 Thread Atish Patra
RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h |

Re: [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor

2022-01-20 Thread Alistair Francis
On Fri, Jan 21, 2022 at 3:16 AM LIU Zhiwei wrote: > > When swap regs for hypervisor, the value of vsstatus or mstatus_hs > should have the right XLEN. Otherwise, it will propagate to mstatus. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 10

Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders

2022-01-20 Thread Philipp Tomsich
On Wed, 19 Jan 2022 at 12:30, Philippe Mathieu-Daudé wrote: > > On 13/1/22 21:20, Philipp Tomsich wrote: > > To split up the decoder into multiple functions (both to support > > vendor-specific opcodes in separate files and to simplify maintenance > > of orthogonal extensions), this changes decode

Re: [PULL v2 00/38] target-arm queue

2022-01-20 Thread Peter Maydell
62963273d7353ce310c82: > > > > Merge remote-tracking branch > > 'remotes/kraxel/tags/seabios-20220118-pull-request' into staging > > (2022-01-19 18:46:28 +) > > > > are available in the Git repository at: > > > > https://git.linaro.org/p

Re: [PULL v2 00/38] target-arm queue

2022-01-20 Thread Peter Maydell
seabios-20220118-pull-request' into staging (2022-01-19 > 18:46:28 +) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20220120-1 > > for you to fetch changes up to b9d383ab797f54ae5fa874

Re: [PATCH] Update copyright dates to 2022

2022-01-20 Thread Philippe Mathieu-Daudé via
On 1/20/22 13:47, Peter Maydell wrote: > It's a new year; update the copyright strings for our > help/version/about information and for our documentation. > > Signed-off-by: Peter Maydell > --- > For once I remembered to do this in January :-) > > I suppose at some point we should try to arrange

[PATCH] configure: fix parameter expansion of --cross-cc-cflags options

2022-01-20 Thread matheus . ferst
From: Matheus Ferst Without this fix, any use of --cross-cc-cflags-* causes a message like: $ ../configure --cross-cc-ppc64le=clang --cross-cc-cflags-ppc64le="-target powerpc64le-unknown-linux-gnu -sysroot ..." ../configure: 1: eval: cross_cc_cflags_--cross-cc-cflags-ppc64le=-target: not found

[RFC 4/5] target/riscv: Add *envcfg* CSRs support

2022-01-20 Thread Atish Patra
The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 31 ++

Re: [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc.

2022-01-20 Thread Peter Maydell
On Tue, 11 Jan 2022 at 08:46, Troy Lee wrote: > > v3: > - Remove unrelated changes to SPI2 address > - Remove controller irq line > > v2: Rebase to mainline QEMU > > Signed-off-by: Troy Lee This turns out not to build on macOS or on 32-bit hosts because of format string issues -- you can't porta

Re: [PATCH] hw/char/exynos4210_uart: Fix crash on trying to load VM state

2022-01-20 Thread Guenter Roeck
On 1/20/22 7:16 AM, Peter Maydell wrote: The exynos4210_uart_post_load() function assumes that it is passed the Exynos4210UartState, but it has been attached to the VMStateDescription for the Exynos4210UartFIFO type. The result is a SIGSEGV when attempting to load VM state for any machine type i

Re: [PATCH v2 5/5] python/aqmp: add socket bind step to legacy.py

2022-01-20 Thread John Snow
On Thu, Jan 20, 2022, 4:13 AM Daniel P. Berrangé wrote: > On Wed, Jan 19, 2022 at 02:39:16PM -0500, John Snow wrote: > > The old QMP library would actually bind to the server address during > > __init__(). The new library delays this to the accept() call, because > > binding occurs inside of the

Re: [PATCH v2 3/6] tests/qtest/libqos: Skip hotplug tests if pci root bus is not hotpluggable

2022-01-20 Thread Alex Bennée
Eric Auger writes: > ARM does not not support hotplug on pcie.0. Add a flag on the bus > which tells if devices can be hotplugged and skip hotplug tests > if the bus cannot be hotplugged. This is a temporary solution to > enable the other pci tests on aarch64. > > Signed-off-by: Eric Auger > A

Re: [PATCH v2 4/6] drop libxml2 checks since libxml is not actually used (for parallels)

2022-01-20 Thread Philippe Mathieu-Daudé via
On 20/1/22 14:37, Thomas Huth wrote: On 20/01/2022 12.05, Philippe Mathieu-Daudé wrote: From: Michael Tokarev For a long time, we assumed that libxml2 is neecessary for parallels Also "necessary", block format support (block/parallels*). However, this format actually does not use libxml [*

[RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.

2022-01-20 Thread Atish Patra
To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. Signed-off

Re: [PATCH 1/3] qsd: Add pre-init argument parsing pass

2022-01-20 Thread Hanna Reitz
On 20.01.22 17:00, Markus Armbruster wrote: Kevin Wolf writes: Am 19.01.2022 um 14:44 hat Hanna Reitz geschrieben: On 19.01.22 13:58, Markus Armbruster wrote: Hanna Reitz writes: We want to add a --daemonize argument to QSD's command line. Why? OK, s/we/I/.  I find it useful, because wi

Re: [PATCH v2] qapi: Cleanup SGX related comments and restore @section-size

2022-01-20 Thread Philippe Mathieu-Daudé via
On 20/1/22 10:10, Daniel P. Berrangé wrote: On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote: The SGX NUMA patches were merged into Qemu 7.0 release, we need clarify detailed version history information and also change some related comments, which make SGX related comments clearer. Th

Re: [PATCH v7 2/4] qapi/monitor: refactor set/expire_password with enums

2022-01-20 Thread Markus Armbruster
Fabian Ebner writes: > Am 21.10.21 um 12:01 schrieb Stefan Reiter: >> 'protocol' and 'connected' are better suited as enums than as strings, >> make use of that. No functional change intended. >> Suggested-by: Markus Armbruster >> Reviewed-by: Markus Armbruster >> Signed-off-by: Stefan Reiter

[PATCH 2/2] iotests: add qcow2-keep-dirty

2022-01-20 Thread Vladimir Sementsov-Ogievskiy
Test new qcow2 open option: keep-dirty. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/tests/qcow2-keep-dirty | 104 ++ tests/qemu-iotests/tests/qcow2-keep-dirty.out | 34 ++ 2 files changed, 138 insertions(+) create mode 100755 tests/qemu-iotests/te

[PATCH 0/2] qcow2: add keep-dirty open option

2022-01-20 Thread Vladimir Sementsov-Ogievskiy
Hi all! Here is suggestion of a new option which we need for our developments in Virtuozzo. For details look at patch 01. Vladimir Sementsov-Ogievskiy (2): qcow2: add keep-dirty open option iotests: add qcow2-keep-dirty qapi/block-core.json | 5 + block/qcow2.h

Re: [PULL 0/3] M68k for 7.0 patches

2022-01-20 Thread Peter Maydell
rectly set the initial PC (2022-01-20 09:09:37 +0100) > > ---- > m68k pull request 20220120 > > Fix virt-m68k reboot > > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0 for any user-visible changes. -- PMM

Re: [PATCH v2 13/14] target/ppc: 405: Program exception cleanup

2022-01-20 Thread Cédric Le Goater
On 1/19/22 13:54, Fabiano Rosas wrote: David Gibson writes: On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote: The 405 Program Interrupt does not set SRR1 with any diagnostic bits, just a clean copy of the MSR. We're using the BookE Exception Syndrome Register which is different

Re: [PATCH] Update copyright dates to 2022

2022-01-20 Thread Daniel P . Berrangé
On Thu, Jan 20, 2022 at 12:47:13PM +, Peter Maydell wrote: > It's a new year; update the copyright strings for our > help/version/about information and for our documentation. > > Signed-off-by: Peter Maydell > --- > For once I remembered to do this in January :-) > > I suppose at some point

[PATCH 1/2] qcow2: add keep-dirty open option

2022-01-20 Thread Vladimir Sementsov-Ogievskiy
Consider the case: Thirdparty component works with qcow2 image, and dirty bit is set. Thirdparty component want to start qemu-img to do some manipulation. Ofcourse, third party component flushes refcounts and other metadata before starting QEMU. But the component don't want to clear dirty bit, a

Re: [PATCH v5 03/18] pci: isolated address space for PCI bus

2022-01-20 Thread Jag Raman
> On Jan 19, 2022, at 7:12 PM, Michael S. Tsirkin wrote: > > On Wed, Jan 19, 2022 at 04:41:52PM -0500, Jagannathan Raman wrote: >> Allow PCI buses to be part of isolated CPU address spaces. This has a >> niche usage. >> >> TYPE_REMOTE_MACHINE allows multiple VMs to house their PCI devices in >

[PATCH] hw/armv7m: Fix broken VMStateDescription

2022-01-20 Thread Peter Maydell
In commit d5093d961585f02 we added a VMStateDescription to the TYPE_ARMV7M object, to handle migration of its Clocks. However a cut-and-paste error meant we used the wrong struct name in the VMSTATE_CLOCK() macro arguments. The result was that attempting a 'savevm' might result in an assertion fail

[PULL v2 00/38] target-arm queue

2022-01-20 Thread Peter Maydell
le in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220120-1 for you to fetch changes up to b9d383ab797f54ae5fa8746117770709921dc529: hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR (2022-01-20 1

Re: [PATCH 0/2] virtio: Add vhost-user-gpio device's support

2022-01-20 Thread Alex Bennée
"Michael S. Tsirkin" writes: > On Thu, Jan 20, 2022 at 09:32:34AM +0530, Viresh Kumar wrote: >> On 17-01-22, 10:11, Alex Bennée wrote: >> > >> > "Michael S. Tsirkin" writes: >> > >> > > On Wed, Jan 12, 2022 at 05:04:57PM +0530, Viresh Kumar wrote: >> > >> Hello, >> > >> >> > >> This patchse

Re: [PATCH v2 2/6] tests/qtest/libqos/pci: Introduce pio_limit

2022-01-20 Thread Alex Bennée
Eric Auger writes: > At the moment the IO space limit is hardcoded to > QPCI_PIO_LIMIT = 0x1. When accesses are performed to a bar, > the base address of this latter is compared against the limit > to decide whether we perform an IO or a memory access. > > On ARM, we cannot keep this PIO li

RE: [PATCH 1/3] migration/migration.c: Add missed default error handler for migration state

2022-01-20 Thread Zhang, Chen
> -Original Message- > From: Dr. David Alan Gilbert > Sent: Thursday, January 20, 2022 1:52 AM > To: Zhang, Chen > Cc: Juan Quintela ; qemu-dev de...@nongnu.org> > Subject: Re: [PATCH 1/3] migration/migration.c: Add missed default error > handler for migration state > > * Zhang Chen

Re: [PATCH v3 10/19] block: introduce fleecing block driver

2022-01-20 Thread Hanna Reitz
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote: Introduce a new driver, that works in pair with copy-before-write to improve fleecing. Without fleecing driver, old fleecing scheme looks as follows: [guest] | |root v [copy-before-write] -> [temp.qcow2] <--- [nbd export] |

Re: [PATCH for-7.0 0/6] target/arm: Implement LVA, LPA, LPA2 features

2022-01-20 Thread Peter Maydell
On Wed, 8 Dec 2021 at 23:14, Richard Henderson wrote: > > These features are all related and relatively small. > > Testing so far has been limited to booting a kernel > with 64k pages and VA and PA set to 52 bits, which > excercises LVA and LPA. > > There is not yet upstream support for LPA2, prob

Re: [PATCH v5 01/18] configure, meson: override C compiler for cmake

2022-01-20 Thread Jag Raman
> On Jan 20, 2022, at 8:27 AM, Paolo Bonzini wrote: > > On 1/19/22 22:41, Jagannathan Raman wrote: >> The compiler path that cmake gets from meson is corrupted. It results in >> the following error: >> | -- The C compiler identification is unknown >> | CMake Error at CMakeLists.txt:35 (project

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