[PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

[Alistair Francis]

From: Frank Chang <frank.ch...@sifive.com>

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.

Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-id: 20220118014522.13613-15-frank.ch...@sifive.com
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index fe4ad5d008..b02bb555a6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2976,6 +2976,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
-- 
2.31.1