Re: [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup

[Cédric Le Goater]

On 1/18/22 19:44, Fabiano Rosas wrote:

The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.

Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
---
  target/ppc/excp_helper.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e4e513322c..13674a102f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -715,7 +715,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int 
excp)

This change is done in the wrong routine.

Thanks,

C.

          break;
      case POWERPC_EXCP_ISI:       /* Instruction storage exception            
*/
          trace_ppc_excp_isi(msr, env->nip);
-        msr |= env->error_code;
          break;
      case POWERPC_EXCP_EXTERNAL:  /* External input                           
*/
      {