From: Alistair Francis <alistair.fran...@wdc.com>
The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827:
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20
16:13:17 +0000)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220121-1
for you to fetch changes up to f297245f6a780f496fb171af6fcd21ff3e6783c3:
target/riscv: Relax UXL field for debugging (2022-01-21 15:52:57 +1000)
----------------------------------------------------------------
Third RISC-V PR for QEMU 7.0
* Fixes for OpenTitan timer
* Correction of OpenTitan PLIC stride length
* RISC-V KVM support
* Device tree code cleanup
* Support for the Zve64f and Zve32f extensions
* OpenSBI binary loading support for the Spike machine
* Removal of OpenSBI ELFs
* Support for the UXL field in xstatus
----------------------------------------------------------------
Anup Patel (3):
hw/riscv: spike: Allow using binary firmware as bios
hw/riscv: Remove macros for ELF BIOS image names
roms/opensbi: Remove ELF images
Frank Chang (17):
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction
insns
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction
insns
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
LIU Zhiwei (23):
target/riscv: Adjust pmpcfg access with mxl
target/riscv: Don't save pc when exception return
target/riscv: Sign extend link reg for jal and jalr
target/riscv: Sign extend pc for different XLEN
target/riscv: Create xl field in env
target/riscv: Ignore the pc bits above XLEN
target/riscv: Extend pc for runtime pc write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Relax debug check for pm write
target/riscv: Adjust csr write mask with XLEN
target/riscv: Create current pm fields in env
target/riscv: Alloc tcg global for cur_pm[mask|base]
target/riscv: Calculate address according to XLEN
target/riscv: Split pm_enabled into mask and base
target/riscv: Split out the vill from vtype
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Remove VILL field in VTYPE
target/riscv: Fix check range for first fault only
target/riscv: Adjust vector address with mask
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Set default XLEN for hypervisor
target/riscv: Enable uxl field write
target/riscv: Relax UXL field for debugging
Thomas Huth (1):
softmmu/device_tree: Silence compiler warning with --enable-sanitizers
Wilfred Mallawa (3):
hw: timer: ibex_timer: Fixup reading w/o register
riscv: opentitan: fixup plic stride len
hw: timer: ibex_timer: update/add reg address
Yanan Wang (1):
softmmu/device_tree: Remove redundant pointer assignment
Yifei Jiang (13):
update-linux-headers: Add asm-riscv/kvm.h
target/riscv: Add target/riscv/kvm.c to place the public kvm interface
target/riscv: Implement function kvm_arch_init_vcpu
target/riscv: Implement kvm_arch_get_registers
target/riscv: Implement kvm_arch_put_registers
target/riscv: Support start kernel directly by KVM
target/riscv: Support setting external interrupt by KVM
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
target/riscv: Add host cpu type
target/riscv: Add kvm_riscv_get/put_regs_timer
target/riscv: Implement virtual time adjusting with vm state changing
target/riscv: Support virtual time context synchronization
target/riscv: enable riscv kvm accel
meson.build | 2 +
include/hw/char/riscv_htif.h | 5 +-
include/hw/riscv/boot.h | 3 +-
include/hw/riscv/spike.h | 1 +
include/hw/timer/ibex_timer.h | 1 -
linux-headers/asm-riscv/kvm.h | 128 ++++++
target/riscv/cpu.h | 58 ++-
target/riscv/cpu_bits.h | 3 +
target/riscv/helper.h | 4 +-
target/riscv/kvm_riscv.h | 25 ++
target/riscv/sbi_ecall_interface.h | 72 ++++
hw/char/riscv_htif.c | 33 +-
hw/intc/sifive_plic.c | 20 +-
hw/riscv/boot.c | 16 +-
hw/riscv/opentitan.c | 2 +-
hw/riscv/spike.c | 45 ++-
hw/riscv/virt.c | 83 ++--
hw/timer/ibex_timer.c | 25 +-
softmmu/device_tree.c | 11 +-
target/riscv/cpu.c | 77 +++-
target/riscv/cpu_helper.c | 99 ++---
target/riscv/csr.c | 90 ++++-
target/riscv/gdbstub.c | 71 +++-
target/riscv/kvm-stub.c | 30 ++
target/riscv/kvm.c | 535 +++++++++++++++++++++++++
target/riscv/machine.c | 46 ++-
target/riscv/op_helper.c | 7 +-
target/riscv/pmp.c | 12 +-
target/riscv/translate.c | 94 +++--
target/riscv/vector_helper.c | 39 +-
target/riscv/insn_trans/trans_privileged.c.inc | 9 +-
target/riscv/insn_trans/trans_rva.c.inc | 9 +-
target/riscv/insn_trans/trans_rvd.c.inc | 19 +-
target/riscv/insn_trans/trans_rvf.c.inc | 19 +-
target/riscv/insn_trans/trans_rvi.c.inc | 39 +-
target/riscv/insn_trans/trans_rvv.c.inc | 225 +++++++++--
.gitlab-ci.d/opensbi.yml | 2 -
pc-bios/meson.build | 2 -
pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes
pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes
roms/Makefile | 2 -
target/riscv/meson.build | 1 +
42 files changed, 1608 insertions(+), 356 deletions(-)
create mode 100644 linux-headers/asm-riscv/kvm.h
create mode 100644 target/riscv/kvm_riscv.h
create mode 100644 target/riscv/sbi_ecall_interface.h
create mode 100644 target/riscv/kvm-stub.c
create mode 100644 target/riscv/kvm.c
delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
