Re: [Qemu-devel] [PATCH] spapr/xive: Add proper rollback to kvmppc_xive_connect()

On Mon, Jul 01, 2019 at 08:13:07AM +0200, Cédric Le Goater wrote: > On 19/06/2019 11:36, David Gibson wrote: > > On Sun, Jun 16, 2019 at 07:22:23PM +0200, Greg Kurz wrote: > >> Make kvmppc_xive_disconnect() able to undo the changes of a partial > >> execution of kvmppc_xive_connect() and use it to

Re: [Qemu-devel] [RFC] Re-evaluating subcluster allocation for qcow2 images

Am 28.06.2019 um 17:12 hat Alberto Garcia geschrieben: > On Fri 28 Jun 2019 05:09:11 PM CEST, Kevin Wolf wrote: > > Am 28.06.2019 um 17:02 hat Alberto Garcia geschrieben: > >> On Fri 28 Jun 2019 04:57:08 PM CEST, Kevin Wolf wrote: > >> > Am 28.06.2019 um 16:43 hat Alberto Garcia geschrieben: > >> >

[Qemu-devel] [QEMU-PPC] [PATCH v3] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

The ibm,get_system_parameter rtas call is used by the guest to retrieve data relating to certain parameters of the system. The SPLPAR characteristics option (token 20) is used to determin characteristics of the environment in which the lpar will run. It may be useful for a guest to know the number

Re: [Qemu-devel] [PATCH] spapr/xive: Add proper rollback to kvmppc_xive_connect()

On 19/06/2019 11:36, David Gibson wrote: > On Sun, Jun 16, 2019 at 07:22:23PM +0200, Greg Kurz wrote: >> Make kvmppc_xive_disconnect() able to undo the changes of a partial >> execution of kvmppc_xive_connect() and use it to perform rollback. >> >> Based-on: <20190614165920.12670-2-...@kaod.org> >>

Re: [Qemu-devel] [PATCH] spapr/xive: H_INT_ESB is used for LSIs only

On 01/07/2019 07:07, David Gibson wrote: > On Fri, Jun 21, 2019 at 05:05:45PM +0200, Cédric Le Goater wrote: >> On 21/06/2019 16:52, Greg Kurz wrote: >>> As indicated in the function header, this "hcall is only supported for >>> LISNs that have the ESB hcall flag set to 1 when returned from hcall()

Re: [Qemu-devel] [PATCH 03/10] ppc/pnv: Rework cache watch model of PnvXIVE

On Sun, Jun 30, 2019 at 10:45:54PM +0200, Cédric Le Goater wrote: > When the software modifies the XIVE internal structures, ESB, EAS, > END, NVT, it also must update the caches of the different XIVE > sub-engines. HW offers a set of common interface for such purpose. > > The CWATCH_SPEC register

Re: [Qemu-devel] [PATCH] spapr_pci: Unregister listeners before destroying the IOMMU address space

On Fri, Jun 21, 2019 at 11:27:33AM +0200, Greg Kurz wrote: > Hot-unplugging a PHB with a VFIO device connected to it crashes QEMU: > > -device spapr-pci-host-bridge,index=1,id=phb1 \ > -device vfio-pci,host=0034:01:00.3,id=vfio0 > > (qemu) device_del phb1 > [ 357.207183] iommu: Removing device 0

Re: [Qemu-devel] [PATCH 01/10] ppc/xive: Force the Physical CAM line value to group mode

On Sun, Jun 30, 2019 at 10:45:52PM +0200, Cédric Le Goater wrote: > When an interrupt needs to be delivered, the XIVE interrupt controller > presenter scans the CAM lines of the thread interrupt contexts of the > HW threads of the chip to find a matching vCPU. The interrupt context > is composed of

Re: [Qemu-devel] [PATCH 02/10] ppc/xive: Make the PIPR register readonly

On Sun, Jun 30, 2019 at 10:45:53PM +0200, Cédric Le Goater wrote: > When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores > its thread interrupt context. The Pending Interrupt Priority Register > (PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores > should not be

Re: [Qemu-devel] [PULL 57/60] target/ppc: add HV support for POWER9

On Fri, Jun 28, 2019 at 03:20:32PM +0200, Philippe Mathieu-Daudé wrote: > Hi, > > On 3/12/19 8:58 PM, Cédric Le Goater wrote: > > On 3/12/19 8:30 PM, Cleber Rosa wrote: > >>> From: "Cleber Rosa" > >>> Sent: Tuesday, March 12, 2019 3:14:09 PM > >>> Subject: Re: [Qemu-devel] [PULL 57/60] target/ppc

Re: [Qemu-devel] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operation

On Sun, Jun 30, 2019 at 10:45:55PM +0200, Cédric Le Goater wrote: > When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the > POOL interrupt context of a CPU with this special command. It returns > the POOL CAM line value and resets the VP bit. > > Fixes: 4836b45510aa ("ppc/xive: act

Re: [Qemu-devel] [PATCH] spapr/xive: H_INT_ESB is used for LSIs only

On Fri, Jun 21, 2019 at 05:05:45PM +0200, Cédric Le Goater wrote: > On 21/06/2019 16:52, Greg Kurz wrote: > > As indicated in the function header, this "hcall is only supported for > > LISNs that have the ESB hcall flag set to 1 when returned from hcall() > > H_INT_GET_SOURCE_INFO". We only set tha

Re: [Qemu-devel] [PATCH 0/2] spapr/xive: rework the mapping the KVM memory regions

On Fri, Jun 14, 2019 at 06:59:18PM +0200, Cédric Le Goater wrote: > Hello, > > Here is a small series simplifying the initialization sequence of the > interrupt device by using memory regions specific for KVM. These are > mapped as overlaps on top of the emulated device. Applied, thanks. > > Th

Re: [Qemu-devel] [QEMU-PPC] [PATCH 1/2] ppc/spapr: Add implementation of hcall H_PURR

On Mon, Jul 01, 2019 at 02:23:21PM +1000, Suraj Jitindar Singh wrote: > On Fri, 2019-06-28 at 19:29 +1000, David Gibson wrote: > > On Mon, Jun 24, 2019 at 03:58:11PM +1000, Suraj Jitindar Singh wrote: > > > The hcall H_PURR is used by a guest to read the PURR (processor > > > utilisation of resourc

[Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 instructions

Add SSE4.1 and SSE4.2 instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 69 1 file changed, 69 insertions(+) diff --git a/x86.risu b/x86.risu index 35992d6..a73e209 100644 --- a/x86.risu +++ b/x86.risu @@

[Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions

Add SSE2 instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 153 +++ 1 file changed, 153 insertions(+) diff --git a/x86.risu b/x86.risu index c29b210..9b63d6b 100644 --- a/x86.risu +++ b/x86.risu @@ -15,179 +15

[Qemu-devel] [RISU RFC PATCH v2 13/14] x86.risu: add AVX instructions

Add AVX instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 288 +++ 1 file changed, 288 insertions(+) diff --git a/x86.risu b/x86.risu index 17a5082..d3115ac 100644 --- a/x86.risu +++ b/x86.risu @@ -17,452 +17,

[Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions

Add an x86 configuration file with all MMX instructions. Signed-off-by: Jan Bobek --- x86.risu | 96 1 file changed, 96 insertions(+) create mode 100644 x86.risu diff --git a/x86.risu b/x86.risu new file mode 100644 index 000..f2dd9b

[Qemu-devel] [RISU RFC PATCH v2 07/14] x86.risu: add SSE instructions

Add SSE instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 100 +++ 1 file changed, 100 insertions(+) diff --git a/x86.risu b/x86.risu index f2dd9b0..c29b210 100644 --- a/x86.risu +++ b/x86.risu @@ -19,6 +19,18

[Qemu-devel] [RISU RFC PATCH v2 10/14] x86.risu: add SSSE3 instructions

Add SSSE3 instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 38 ++ 1 file changed, 38 insertions(+) diff --git a/x86.risu b/x86.risu index 01181dd..35992d6 100644 --- a/x86.risu +++ b/x86.risu @@ -77,6 +77,13 @@ ADDPD

[Qemu-devel] [RISU RFC PATCH v2 14/14] x86.risu: add AVX2 instructions

Add AVX2 instructions to the configuration file. Signed-off-by: Jan Bobek --- x86.risu | 257 +++ 1 file changed, 257 insertions(+) diff --git a/x86.risu b/x86.risu index d3115ac..74c4ce8 100644 --- a/x86.risu +++ b/x86.risu @@ -33,16 +33,22 @

[Qemu-devel] [RISU RFC PATCH v2 05/14] risugen: allow all byte-aligned instructions

Accept all instructions whose bit length is divisible by 8. Note that the maximum instruction length (as specified in the config file) is 32 bits, hence this change permits instructions which are 8 bits or 24 bits long (16-bit instructions have already been considered valid). Note that while valid

[Qemu-devel] [RISU RFC PATCH v2 01/14] risugen_common: add insnv, randint_constr, rand_fill

Add three common utility functions: - insnv allows emitting variable-length instructions in little-endian or big-endian byte order; it subsumes functionality of former insn16() and insn32() functions. - randint_constr allows generating random integers according to several constraints passed

[Qemu-devel] [RISU RFC PATCH v2 09/14] x86.risu: add SSE3 instructions

Add SSE3 instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 14 ++ 1 file changed, 14 insertions(+) diff --git a/x86.risu b/x86.risu index 9b63d6b..01181dd 100644 --- a/x86.risu +++ b/x86.risu @@ -49,6 +49,11 @@ PMOVMSKBSSE2 11010

[Qemu-devel] [RISU RFC PATCH v2 04/14] risugen_x86: add module

The risugen_x86.pm module contains most of the code specific to Intel i386 and x86_64 architectures. This commit also adds --x86_64 option, which enables emission of 64-bit (rather than 32-bit) assembly. Signed-off-by: Jan Bobek --- risugen| 6 +- risugen_x86.pm | 498 +

[Qemu-devel] [RISU RFC PATCH v2 02/14] risugen_x86_asm: add module

The module risugen_x86_asm.pm exports several constants and the function write_insn, which work in tandem to allow emission of x86 instructions in more clear and structured manner. Signed-off-by: Jan Bobek --- risugen_x86_asm.pm | 252 + 1 file changed

[Qemu-devel] [RISU RFC PATCH v2 03/14] risugen_x86_emit: add module

The helper module risugen_x86_emit.pm exports a single function "parse_emitblock", which serves to capture and return instruction constraints described by "emit" blocks in an x86 configuration file. Signed-off-by: Jan Bobek --- risugen | 2 +- risugen_x86_emit.pm | 91 ++

[Qemu-devel] [RISU RFC PATCH v2 00/14] Support for generating x86 MMX/SSE/AVX test images

This is a v2 of the patch series first posted in [1]. This version also implements the VEX prefix, hence all SIMD extensions up to AVX2 are supported. Notable exceptions are LDMXCSR (cannot constrain memory contents yet) and all forms of VGATHER (VSIB not implemented). Note that this is still not

Re: [Qemu-devel] [QEMU-PPC] [PATCH 1/2] ppc/spapr: Add implementation of hcall H_PURR

On Fri, 2019-06-28 at 19:29 +1000, David Gibson wrote: > On Mon, Jun 24, 2019 at 03:58:11PM +1000, Suraj Jitindar Singh wrote: > > The hcall H_PURR is used by a guest to read the PURR (processor > > utilisation of resources register). A guest expects that this > > register > > will count at a rate

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On Jun 30, 2019 5:12 PM, "Richard Henderson" wrote: > > On 6/30/19 3:37 PM, Aleksandar Markovic wrote: > >> bool have_isa_2_06; > >> bool have_isa_2_06_vsx; > >> +bool have_isa_2_07_vsx; > > > > Does this flag indicate support for PowerISA 2.07 or VSX? > > VSX & 2.07, > > >> +if (hwcap2 & PP

Re: [Qemu-devel] [PATCH v2 0/7] Qemu virtio pmem device

Ping. > > This patch series has implementation for "virtio pmem" > device. "virtio pmem" is persistent memory(nvdimm) device in > guest which allows to bypass the guest page cache. This > also implements a VIRTIO based asynchronous flush mechanism. > Details of project idea for 'virtio pme

Re: [Qemu-devel] [RFC 1/1] hw/pvrdma: Add live migration support

On Sun, 30 Jun 2019 at 13:43, Yuval Shaia wrote: > > On Sat, Jun 29, 2019 at 06:15:21PM +0530, Sukrit Bhatnagar wrote: > > On Fri, 28 Jun 2019 at 16:56, Dr. David Alan Gilbert > > wrote: > > > > > > * Yuval Shaia (yuval.sh...@oracle.com) wrote: > > > > On Fri, Jun 21, 2019 at 08:15:41PM +0530, Su

Re: [Qemu-devel] [PATCH v5 4/8] numa: move numa global variable numa_info into MachineState

On 6/28/2019 7:20 PM, Igor Mammedov wrote: On Fri, 14 Jun 2019 23:56:22 +0800 Tao Xu wrote: Move existing numa global numa_info (renamed as "nodes") into NumaState. Reviewed-by: Liu Jingqi Suggested-by: Igor Mammedov Suggested-by: Eduardo Habkost Signed-off-by: Tao Xu --- Changes in v5 -

Re: [Qemu-devel] [PATCH v5 2/8] numa: move numa global variable nb_numa_nodes into MachineState

On 6/28/2019 7:02 PM, Igor Mammedov wrote: On Fri, 14 Jun 2019 23:56:20 +0800 Tao Xu wrote: Add struct NumaState in MachineState and move existing numa global nb_numa_nodes(renamed as "num_nodes") into NumaState. And add variable numa_support into MachineClass to decide which submachines suppo

Re: [Qemu-devel] [PATCH v5 6/8] hmat acpi: Build Memory Subsystem Address Range Structure(s) in ACPI HMAT

On 6/27/2019 11:56 PM, Jonathan Cameron wrote: On Fri, 14 Jun 2019 23:56:24 +0800 Tao Xu wrote: From: Liu Jingqi HMAT is defined in ACPI 6.2: 5.2.27 Heterogeneous Memory Attribute Table (HMAT). The specification references below link: http://www.uefi.org/sites/default/files/resources/ACPI_6_

Re: [Qemu-devel] [PATCH 1/2] tests/acceptance: Add test of NeXTcube framebuffer using OCR

On 6/30/19 9:08 PM, Thomas Huth wrote: > On 29/06/2019 17.00, Philippe Mathieu-Daudé wrote: >> Add a test of the NeXTcube framebuffer using the Tesseract OCR >> engine on a screenshot of the framebuffer device. > > Wow, that's a funny idea, I like it! > >> The test is very quick: >> >> $ avocad

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

On Sat, Jun 29, 2019 at 12:17:22AM +0200, Paolo Bonzini wrote: > On 28/06/19 16:06, Michael S. Tsirkin wrote: > >> +assert(kvm_irqchip_in_kernel()); > > Hmm - irqchip in kernel actually increases the attack surface, > > does it not? Or at least, the severity of the attacks. > > Yeah, we should

Re: [Qemu-devel] [PATCH 2/4] hw/virtio: Factorize virtio-mmio headers

On Fri, Jun 28, 2019 at 10:50:47PM +0200, Sergio Lopez wrote: > > Michael S. Tsirkin writes: > > > On Fri, Jun 28, 2019 at 01:53:47PM +0200, Sergio Lopez wrote: > >> Put QOM and main struct definition in a separate header file, so it > >> can be accesed from other components. > >> > >> This is

Re: [Qemu-devel] [PATCH] pc: Move compat_apic_id_mode variable to PCMachineClass

On Fri, Jun 28, 2019 at 05:02:27PM -0300, Eduardo Habkost wrote: > Replace the static variable with a PCMachineClass field. This > will help us eventually get rid of the pc_compat_*() init > functions. > > Signed-off-by: Eduardo Habkost Reviewed-by: Michael S. Tsirkin Pls feel free to merge.

[Qemu-devel] [PATCH 06/10] ppc/xive: Provide escalation support

If the XIVE presenter can not find the NVT dispatched on any of the HW threads, it can not deliver the interrupt. XIVE offers a mechanism to handle such scenarios and inform the hypervisor that an action should be taken. The first action is to keep track of the pending priority of the missed event

[Qemu-devel] [PATCH 08/10] ppc/xive: Extend XiveTCTX with an router object pointer

This is to perform lookups in the NVT table when a vCPU is dispatched and possibly resend interrupts. Future XIVE chip will use a different class for the model of the interrupt controller. So use an 'Object *' instead of a 'XiveRouter *'. Signed-off-by: Cédric Le Goater --- include/hw/ppc/xive.

[Qemu-devel] [PATCH 07/10] ppc/xive: Improve 'info pic' support

Provide a better output of the XIVE END structures including the escalation information and extend the PowerNV machine 'info pic' command with a dump of the END EAS table used for escalations. Signed-off-by: Cédric Le Goater --- include/hw/ppc/xive.h | 5 include/hw/ppc/xive_regs.h |

[Qemu-devel] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operation

When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the POOL interrupt context of a CPU with this special command. It returns the POOL CAM line value and resets the VP bit. Fixes: 4836b45510aa ("ppc/xive: activate HV support") Signed-off-by: Cédric Le Goater --- hw/intc/xive.c | 19

[Qemu-devel] [PATCH 05/10] ppc/xive: Implement TM_PULL_OS_CTX special command

When a vCPU is not dispatched anymore on a HW thread, the Hypervisor (KVM) invalidates the OS interrupt context of a vCPU with this special command. It returns the OS CAM line value and resets the VO bit. Signed-off-by: Cédric Le Goater --- hw/intc/xive.c | 15 ++- 1 file changed, 14

[Qemu-devel] [PATCH 10/10] ppc/pnv: Dump the XIVE NVT table

This is to track the configuration of the base END index of the vCPU and the Interrupt Pending Buffer. The NVT IPB is updated when an interrupt can not be presented to a vCPU. We try to loop on the full table skipping empty indirect pages which are not necessarily allocated. Signed-off-by: Cédric

[Qemu-devel] [PATCH 02/10] ppc/xive: Make the PIPR register readonly

When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores its thread interrupt context. The Pending Interrupt Priority Register (PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores should not be allowed to change its value. Fixes: 207d9fe98510 ("ppc/xive: introduce t

[Qemu-devel] [PATCH 09/10] ppc/xive: Synthesize interrupt from the saved IPB in the NVT

When an interrupt can not be presented to a vCPU, the XIVE presenter updates the Interrupt Pending Buffer of the XIVE NVT if backlog is activated in the END. Later, when the same vCPU is dispatched, its context is pushed in the thread context registers and the VO bit is set in the CAM line word. T

[Qemu-devel] [PATCH 03/10] ppc/pnv: Rework cache watch model of PnvXIVE

When the software modifies the XIVE internal structures, ESB, EAS, END, NVT, it also must update the caches of the different XIVE sub-engines. HW offers a set of common interface for such purpose. The CWATCH_SPEC register defines the block/index of the target and a set of flags to perform a full u

[Qemu-devel] [PATCH 01/10] ppc/xive: Force the Physical CAM line value to group mode

When an interrupt needs to be delivered, the XIVE interrupt controller presenter scans the CAM lines of the thread interrupt contexts of the HW threads of the chip to find a matching vCPU. The interrupt context is composed of 4 different sets of registers: Physical, HV, OS and User. The encoding o

[Qemu-devel] [PATCH 00/10] ppc/pnv: add XIVE support for KVM guests

Hello, The QEMU PowerNV machine emulates a baremetal OpenPOWER system and acts as an hypervisor (L0). Supporting emulation of KVM to run guests (L1) requires a few more extensions, among which support for the XIVE interrupt controller on POWER9 processor. The following changes fix some parts of

Re: [Qemu-devel] [PATCH 1/2] tests/acceptance: Add test of NeXTcube framebuffer using OCR

On 29/06/2019 17.00, Philippe Mathieu-Daudé wrote: > Add a test of the NeXTcube framebuffer using the Tesseract OCR > engine on a screenshot of the framebuffer device. Wow, that's a funny idea, I like it! > The test is very quick: > > $ avocado --show=app,ocr run tests/acceptance/machine_m68k_

Re: [Qemu-devel] [PATCH 2/2] Acceptance tests: add SPICE protocol check

On Fri, Jun 28, 2019 at 05:54:37PM -0300, Wainer dos Santos Moschetta wrote: > > On 06/21/2019 03:09 AM, Cleber Rosa wrote: > > This fires a QEMU binary with SPICE enabled, and does a basic > > handshake, doing a basic client/server interaction and protocol > > validation. > > > > Signed-off-by:

Re: [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes

On 29/06/2019 14:00, Richard Henderson wrote: > Changes since v5: > * Disable runtime altivec detection until all of the required > opcodes are implemented. > Because dup2 was last, that really means all of the pure altivec > bits, so the initial patches are not bisectable in any mea

Re: [Qemu-devel] [PATCH 1/2] Acceptance tests: exclude "flaky" tests

On Fri, Jun 28, 2019 at 05:43:09PM -0300, Wainer dos Santos Moschetta wrote: > > On 06/21/2019 11:38 AM, Cleber Rosa wrote: > > On Fri, Jun 21, 2019 at 09:03:33AM +0200, Philippe Mathieu-Daudé wrote: > > > On 6/21/19 8:09 AM, Cleber Rosa wrote: > > > > It's a fact that some tests may not be 100% r

Re: [Qemu-devel] [PATCH 3/3] tests/acceptance: Add boot linux with kvm test

On Fri, Jun 28, 2019 at 05:18:46PM -0300, Eduardo Habkost wrote: > On Fri, Jun 28, 2019 at 11:02:17AM -0400, Wainer dos Santos Moschetta wrote: > > Until now the suite of acceptance tests doesn't exercise > > QEMU with kvm enabled. So this introduces a simple test > > that boots the Linux kernel an

[Qemu-devel] [PATCH 1/5] sunhme: add trace event for logging PCI IRQ

Signed-off-by: Mark Cave-Ayland --- hw/net/sunhme.c | 2 ++ hw/net/trace-events | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c index 1ebaee3c82..6d660a8238 100644 --- a/hw/net/sunhme.c +++ b/hw/net/sunhme.c @@ -209,6 +209,8 @@ static void sunhme_update

[Qemu-devel] [PATCH 5/5] sunhme: ensure that RX descriptor ring overflow is indicated to client driver

On very busy networks connected via a tap interface, it is possible to overflow the RX descriptor ring in the time between the client driver enabling the RX MAC and finishing writing the final configuration to the NIC registers. Ensure that we detect this condition and update the status register a

[Qemu-devel] [PATCH 4/5] sunhme: fix return values from sunhme_receive() during receive packet processing

The current return values in sunhme_receive() when processing incoming packets are inverted from what they should be. Make sure that we return 0 to indicate the packet was discarded (and polling is to be disabled) and -1 to indicate that the packet was discarded but polling for incoming data is to

[Qemu-devel] [PATCH 2/5] sunhme: fix incorrect constant in sunhme_can_receive()

Due to a copy/paste error the wrong register was being checked in order to determine if the NIC is able to receive data. Signed-off-by: Mark Cave-Ayland --- hw/net/sunhme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c index 6d660a8238..e3a

[Qemu-devel] [PATCH 0/5] sunhme: misc fixes for tap mode

This patchset contains a set of fixes found whilst investigating some privately reported issues when using the sunhme device in tap mode on a busy network. The first patch simply adds a trace-event for logging the PCI IRQ which was useful in help diagnose the issues in the subsequent patches. Pat

[Qemu-devel] [PATCH 3/5] sunhme: flush any queued packets when HME_MAC_RXCFG_ENABLE bit is raised

Some client drivers use this bit to pause and resume the driver so make sure that queued packets are flushed when the MAC is disabled and then reactivated. Signed-off-by: Mark Cave-Ayland --- hw/net/sunhme.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/net/sunhme.c b/hw/net

Re: [Qemu-devel] [PATCH v16 1/5] linux-user: Add support for translation of statx() syscall

On Jun 29, 2019 6:06 AM, "Jim Wilson" wrote: > > On Fri, Jun 28, 2019 at 5:53 PM Aleksandar Markovic > wrote: > > This patch went trough several transformations in last few days, and I am a little worried that we forgot the primary reasons/scenarios why want it in the first place. In that light,

[Qemu-devel] [PATCH] hw/arm/virt: Add support for Cortex-A7

From: Jan Kiszka No reason to deny this type. Signed-off-by: Jan Kiszka --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 431e2900fd..ed009fa447 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -176,6 +176,7 @@ static const int a15irqmap

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On 6/30/19 3:37 PM, Aleksandar Markovic wrote: >>  bool have_isa_2_06; >>  bool have_isa_2_06_vsx; >> +bool have_isa_2_07_vsx; > > Does this flag indicate support for PowerISA 2.07 or VSX? VSX & 2.07, >> +    if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { >> +        if (hwcap & PPC_FEATURE_HAS_VSX) { >

[Qemu-devel] [PATCH 1/1] raw-posix.c - use max transfer length / max segemnt count only for SCSI passthrough

Regular block devices (/dev/sda*, /dev/nvme*, etc) interface is not limited by the underlying storage limits, but rather the kernel block layer takes care to split the requests that are too large/fragmented. Doing so allows us to have less overhead in qemu. Signed-off-by: Maxim Levitsky --- blo

[Qemu-devel] [PATCH 0/1] RFC: don't obey the block device max transfer len / max segments for block devices

It looks like Linux block devices, even in O_DIRECT mode don't have any user visible limit on transfer size / number of segments, which underlying block device can have. The block layer takes care of enforcing these limits by splitting the bios. By limiting the transfer sizes, we force qemu to

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On Jun 29, 2019 3:14 PM, "Richard Henderson" wrote: > > This includes single-word loads and stores, lots of double-word > arithmetic, and a few extra logical operations. > > Signed-off-by: Richard Henderson > Signed-off-by: Aleksandar Markovic > --- > tcg/ppc/tcg-target.h | 3 +- > tcg/pp

Re: [Qemu-devel] [PATCH v6 15/16] tcg/ppc: Update vector support to v2.07

On Jun 29, 2019 3:14 PM, "Richard Henderson" wrote: > > This includes single-word loads and stores, lots of double-word > arithmetic, and a few extra logical operations. > This patch should be split into several units (so, treat shift, compare, etc. separately). The same for other similar patche

Re: [Qemu-devel] [PATCH v6 04/16] tcg/ppc: Enable tcg backend vector compilation

On Jun 30, 2019 12:48 PM, "Richard Henderson" wrote: > > On 6/30/19 11:46 AM, Aleksandar Markovic wrote: > > > > > > On Saturday, June 29, 2019, Richard Henderson < richard.hender...@linaro.org > > > wrote: > > > > Introduce all of the flags required to ena

Re: [Qemu-devel] [PATCH v6 09/16] tcg/ppc: Prepare case for vector multiply

On Jun 30, 2019 12:49 PM, "Richard Henderson" wrote: > > On 6/30/19 11:52 AM, Aleksandar Markovic wrote: > > > > > > On Saturday, June 29, 2019, Richard Henderson < richard.hender...@linaro.org > > > wrote: > > > > This line is just preparation for full vec

Re: [Qemu-devel] [PATCH v6 04/16] tcg/ppc: Enable tcg backend vector compilation

On 6/30/19 11:46 AM, Aleksandar Markovic wrote: > > > On Saturday, June 29, 2019, Richard Henderson > wrote: > > Introduce all of the flags required to enable tcg backend vector support, > and a runtime flag to indicate the host supports Altivec inst

Re: [Qemu-devel] [PATCH v6 09/16] tcg/ppc: Prepare case for vector multiply

On 6/30/19 11:52 AM, Aleksandar Markovic wrote: > > > On Saturday, June 29, 2019, Richard Henderson > wrote: > > This line is just preparation for full vector multiply support > in some of subsequent patches. > > > This patch should be aquashed int

[Qemu-devel] [PATCH v9 1/2] hw/arm: Add arm SBSA reference machine, skeleton part

For the Aarch64, there is one machine 'virt', it is primarily meant to run on KVM and execute virtualization workloads, but we need an environment as faithful as possible to physical hardware, for supporting firmware and OS development for pysical Aarch64 machines. This patch introduces new machin

[Qemu-devel] [PATCH v9 0/2] Add Arm SBSA Reference Machine

For the Aarch64, there is one machine 'virt', it is primarily meant to run on KVM and execute virtualization workloads, but we need an environment as faithful as possible to physical hardware, to support firmware and OS development for pysical Aarch64 machines. This machine comes with: - Re-desi

[Qemu-devel] [PATCH v9 2/2] hw/arm: Add arm SBSA reference machine, devices part

Following the previous patch, this patch adds peripheral devices to the newly introduced SBSA-ref machine. Signed-off-by: Hongbo Zhang --- hw/arm/sbsa-ref.c | 525 ++ 1 file changed, 525 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sb

Re: [Qemu-devel] [PATCH v6 09/16] tcg/ppc: Prepare case for vector multiply

On Saturday, June 29, 2019, Richard Henderson wrote: > This line is just preparation for full vector multiply support > in some of subsequent patches. > > This patch should be aquashed into the patch on implementing multiply. > Signed-off-by: Richard Henderson > Signed-off-by: Aleksandar Mark

Re: [Qemu-devel] [PATCH v6 04/16] tcg/ppc: Enable tcg backend vector compilation

On Saturday, June 29, 2019, Richard Henderson wrote: > Introduce all of the flags required to enable tcg backend vector support, > and a runtime flag to indicate the host supports Altivec instructions. > > If two flags have different purpose and usage, it is better that they have different names.

Re: [Qemu-devel] [PATCH v8 2/2] hw/arm: Add arm SBSA reference machine, devices part

On Sun, 23 Jun 2019 at 10:42, Hongbo Zhang wrote: > > Following the previous patch, this patch adds peripheral devices to the > newly introduced SBSA-ref machine. > > Signed-off-by: Hongbo Zhang > --- > hw/arm/sbsa-ref.c | 523 > +- > 1 file c

Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

On 6/29/19 6:36 PM, Lucien Murray-Pitts wrote: > On Sat, Jun 29, 2019 at 12:15:44PM +0200, Richard Henderson wrote: >> On 6/28/19 5:50 PM, Lucien Murray-Pitts wrote: >>> op_helper.c >>>static void m68k_interrupt_all(CPUM68KState *env, int is_hw) >>>... >>> if (cs->exception_index == E

Re: [Qemu-devel] [RFC 1/1] hw/pvrdma: Add live migration support

On Sat, Jun 29, 2019 at 06:15:21PM +0530, Sukrit Bhatnagar wrote: > On Fri, 28 Jun 2019 at 16:56, Dr. David Alan Gilbert > wrote: > > > > * Yuval Shaia (yuval.sh...@oracle.com) wrote: > > > On Fri, Jun 21, 2019 at 08:15:41PM +0530, Sukrit Bhatnagar wrote: > > > > Define and register SaveVMHandlers

Re: [Qemu-devel] [PATCH v3 0/7] Kconfig dependencies for MIPS machines (but Malta)

On Mar 11, 2019 1:56 AM, "Philippe Mathieu-Daudé" wrote: > > Express the MIPS machine dependencies with Kconfig. > > Due to its complexity, the Malta board fill follow in a different > series. > Philippe, What do we do with this series for 4.1? Yours, Aleksandar > v3: > - addressed review comm