On Sun, Jun 30, 2019 at 10:45:52PM +0200, Cédric Le Goater wrote:
> When an interrupt needs to be delivered, the XIVE interrupt controller
> presenter scans the CAM lines of the thread interrupt contexts of the
> HW threads of the chip to find a matching vCPU. The interrupt context
> is composed of 4 different sets of registers: Physical, HV, OS and
> User.
>
> The encoding of the Physical CAM line depends on the mode in which the
> interrupt controller is operating: CAM mode or block group mode.
> Block group mode being the default configuration today on POWER9 and
> the only one available on the next POWER10 generation, enforce this
> encoding in the Physical CAM line :
>
> chip << 19 | 0000000 0 0001 thread (7Bit)
>
> It fits the overall encoding of the NVT ids and simplifies the matching
> algorithm in the presenter.
>
> Fixes: d514c48d41fb ("ppc/xive: hardwire the Physical CAM line of the thread
> context")
> Signed-off-by: Cédric Le Goater <c...@kaod.org>
Since this appears to be a fix, applied to ppc-for-4.1.
> ---
> hw/intc/xive.c | 21 +++++----------------
> 1 file changed, 5 insertions(+), 16 deletions(-)
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 6250c0414de8..3b1f9520ae9f 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -1229,27 +1229,16 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr,
> CPUState *cs)
> }
>
> /*
> - * By default on P9, the HW CAM line (23bits) is hardwired to :
> + * Encode the HW CAM line in the block group mode format :
> *
> - * 0x000||0b1||4Bit chip number||7Bit Thread number.
> - *
> - * When the block grouping is enabled, the CAM line is changed to :
> - *
> - * 4Bit chip number||0x001||7Bit Thread number.
> + * chip << 19 | 0000000 0 0001 thread (7Bit)
> */
> -static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid)
> -{
> - return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f);
> -}
> -
> -static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx,
> - uint8_t nvt_blk, uint32_t nvt_idx)
> +static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
> {
> CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
> uint32_t pir = env->spr_cb[SPR_PIR].default_value;
>
> - return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) ==
> - hw_cam_line(nvt_blk, nvt_idx);
> + return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
> }
>
> /*
> @@ -1285,7 +1274,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx,
> uint8_t format,
>
> /* PHYS ring */
> if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
> - xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) {
> + cam == xive_tctx_hw_cam_line(tctx)) {
> return TM_QW3_HV_PHYS;
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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