Hello, The QEMU PowerNV machine emulates a baremetal OpenPOWER system and acts as an hypervisor (L0). Supporting emulation of KVM to run guests (L1) requires a few more extensions, among which support for the XIVE interrupt controller on POWER9 processor.
The following changes fix some parts of the XIVE model and provide support for escalations and resend. This mechanism is used by KVM to kick a vCPU when it is not dispatched on a HW thread. A series from Suraj adding guest support in the Radix MMU model of the QEMU PowerNV machine is still required and will be send later. The whole patchset can be found under : https://github.com/legoater/qemu/tree/powernv-4.1 Thanks, C. Cédric Le Goater (10): ppc/xive: Force the Physical CAM line value to group mode ppc/xive: Make the PIPR register readonly ppc/pnv: Rework cache watch model of PnvXIVE ppc/xive: Fix TM_PULL_POOL_CTX special operation ppc/xive: Implement TM_PULL_OS_CTX special command ppc/xive: Provide escalation support ppc/xive: Improve 'info pic' support ppc/xive: Extend XiveTCTX with an router object pointer ppc/xive: Synthesize interrupt from the saved IPB in the NVT ppc/pnv: Dump the XIVE NVT table include/hw/ppc/xive.h | 23 ++- include/hw/ppc/xive_regs.h | 13 ++ hw/intc/pnv_xive.c | 211 +++++++++++++++++++---- hw/intc/spapr_xive.c | 1 - hw/intc/xive.c | 341 +++++++++++++++++++++++++++++-------- hw/ppc/pnv.c | 2 +- hw/ppc/spapr_irq.c | 2 +- 7 files changed, 479 insertions(+), 114 deletions(-) -- 2.21.0
