[Mesa-dev] [v2 04/12] i965: Move texture buffer dispatch into single location

All generations do the same exact dispatch and it could be therefore done in the hardware independent stage. Reviewed-by: Matt Turner Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 3 --- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 07/12] i965: Move texture swizzle resolving into dispatcher

Reviewed-by: Matt Turner Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 +++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 17

[Mesa-dev] [v2 12/12] i965/SQUASH: Implement surface state set-up for shader images.

--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 6e0166e..250c61a 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 11/12] i965: Implement surface state set-up for shader images.

From: Francisco Jerez --- src/mesa/drivers/dri/i965/brw_context.h | 2 + src/mesa/drivers/dri/i965/brw_surface_formats.c | 112 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 77 3 files changed, 191 insertions(+) diff --git a/src/mesa/d

[Mesa-dev] [v2 06/12] i965: Move tex miptree and format resolving into dispatcher

All hardware platforms have this in common, so do it in the hardware independent dispatcher. v2 (Matt): Removed extra whitespace. Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4

[Mesa-dev] [v2 03/12] i965/gen7: Check mip-tree for integer formats in surface setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 1527d12..60f9228 100644 --- a/src

[Mesa-dev] [v2 10/12] i965: Pass slice details as parameters for surface setup

t for ILK in the surface setup. v2: - Removed extra whitespace and switched tabs to spaces (Matt) - Added assertion on minimum level (Ken). Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h

[Mesa-dev] [v2 05/12] i965/gen8: Use miptree format in the surface setup

urner Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 304e5fe..5a

[Mesa-dev] [v2 08/12] i965: Refactor effective depth calculation

Reviewed-by: Matt Turner Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +-- src/mesa

[Mesa-dev] [PATCH] i965/wm/gen6: Refactor state setup

CC: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_state.h | 11 +++ src/mesa/drivers/dri/i965/gen6_wm_state.c | 111 ++ 2 files changed, 77 insertions(+), 45 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_stat

[Mesa-dev] [PATCH] i965/wm/gen6: Add option for disabling statistics collection

Normally this always needed but for internal blits and clears we need to be able to disable it. CC: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_state.h | 3 ++- src/mesa/drivers/dri/i965/gen6_wm_state.c | 14 +++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH] i965/wm/gen7: Refactor state setup

CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 9 +++ src/mesa/drivers/dri/i965/gen7_wm_state.c | 98 --- 2 files changed, 74 insertions(+), 33 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b

[Mesa-dev] [RFC 01/16] glsl: Add tracking for GLSL precision qualifiers

From: Iago Toral Quiroga Currently, we only consider precision qualifiers at compile-time. This patch adds precision information to ir_variable so we can also do link time checks. Specifically, from the GLSL ES3 spec, 4.5.3 Precision Qualifiers: "The same uniform declared in different shaders th

[Mesa-dev] [RFC 12/16] nir: Consider float precision when deciding between int/float: part2

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/glsl_to_nir.cpp | 61 ++-- 1 file changed, 25 insertions(+), 36 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 1267475..5b3c2ad 100644 --- a/src/glsl/nir

[Mesa-dev] [RFC 15/16] nir: Consider float precision when deciding opcode

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/glsl_to_nir.cpp | 61 +--- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 4cb250a..b4777aa 100644 --- a/src/glsl/nir

[Mesa-dev] [RFC 03/16] mesa: Add half float uniform support

Signed-off-by: Topi Pohjolainen --- src/mesa/main/uniform_query.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index 728bd1b..4cdb682 100644 --- a/src/mesa/main/uniform_query.cpp +++ b/src/mesa/main

[Mesa-dev] [RFC 08/16] glsl: Add support for half float loop control

Signed-off-by: Topi Pohjolainen --- src/glsl/loop_controls.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/loop_controls.cpp b/src/glsl/loop_controls.cpp index 51804bb..4ba3049 100644 --- a/src/glsl/loop_controls.cpp +++ b/src/glsl/loop_controls.cpp @@ -132,6 +132,7

[Mesa-dev] [RFC 13/16] nir: Consider float precision when deciding between uint/int/float

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/glsl_to_nir.cpp | 55 +++- 1 file changed, 13 insertions(+), 42 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 5b3c2ad..5da4122 100644 --- a/src/glsl/nir

[Mesa-dev] [RFC 09/16] glsl/ast: Use half float type for medium and low precisions

Signed-off-by: Topi Pohjolainen --- src/glsl/ast_to_hir.cpp | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 332de5b..a8909ce 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp

[Mesa-dev] [RFC 05/16] glsl: Allow half float type to be used where-ever float is supported

Signed-off-by: Topi Pohjolainen --- src/glsl/glsl_types.h| 2 +- src/glsl/ir_validate.cpp | 36 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/src/glsl/glsl_types.h b/src/glsl/glsl_types.h index d58718e..b90aa28 100644 --- a/src/glsl

[Mesa-dev] [RFC 04/16] glsl: Add half float type generation

Signed-off-by: Topi Pohjolainen --- src/glsl/builtin_type_macros.h | 16 +++ src/glsl/builtin_types.cpp | 31 + src/glsl/glsl_types.cpp| 44 +++--- src/glsl/glsl_types.h | 6 +- 4 files changed

[Mesa-dev] [RFC 07/16] glsl: Add ubo lowering support for half floats

Signed-off-by: Topi Pohjolainen --- src/glsl/lower_ubo_reference.cpp | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp index 4ea4ccb..15e783b 100644 --- a/src/glsl/lower_ubo_reference.cpp +++ b/src

[Mesa-dev] [RFC 10/16] nir: Introduce half float opcodes

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/nir.h | 2 + src/glsl/nir/nir_constant_expressions.py | 8 +++- src/glsl/nir/nir_opcodes.py | 78 +++- 3 files changed, 86 insertions(+), 2 deletions(-) diff --git a/src/glsl/nir

[Mesa-dev] [RFC 14/16] nir: Consider float precision when deciding between uint/float

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/glsl_to_nir.cpp | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 5da4122..4cb250a 100644 --- a/src/glsl/nir/glsl_to_nir.cpp +++ b/src/glsl/nir

[Mesa-dev] [RFC 11/16] nir: Consider float precision when deciding between int/float

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/glsl_to_nir.cpp | 39 +-- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 7a20e1a..1267475 100644 --- a/src/glsl/nir

[Mesa-dev] RFC: Supporting mediump in NIR

One natural place would be in patch number nine. This is just one example of details missing in the proposal - these patches are only meant to give a rough idea how the approach chosen would look like. Iago Toral Quiroga (1): glsl: Add tracking for GLSL precision qualifiers Topi Pohjolainen (15):

[Mesa-dev] [RFC 06/16] glsl: Add support for half floats in optimization passes

Signed-off-by: Topi Pohjolainen --- src/glsl/ir_print_visitor.cpp | 1 + src/glsl/opt_algebraic.cpp| 11 --- src/glsl/opt_constant_propagation.cpp | 1 + src/glsl/opt_minmax.cpp | 2 ++ 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a

[Mesa-dev] [RFC 16/16] nir: Consider float precision when deciding opcode: part 2

Signed-off-by: Topi Pohjolainen --- src/glsl/nir/glsl_to_nir.cpp | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index b4777aa..14c4324 100644 --- a/src/glsl/nir/glsl_to_nir.cpp

[Mesa-dev] [RFC 02/16] glsl: Add half float type

Signed-off-by: Topi Pohjolainen --- src/glsl/ast_to_hir.cpp| 1 + src/glsl/glsl_types.cpp| 2 ++ src/glsl/glsl_types.h | 9 + src/glsl/ir_clone.cpp | 1 + src/glsl

[Mesa-dev] [RFC] i965: Don't consider uniform value locations in program uploads

etc) let alone its target precision. No regression in jenkins. However, we talked about this with Ken and this doesn't really tell much as piglit doesn't really re-use shader sources during one execution. Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke CC: Tapani P\344lli ---

[Mesa-dev] [WIP 02/25] mesa: Teach uniform update to take into account double precision

Signed-off-by: Topi Pohjolainen --- src/mesa/main/uniform_query.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index f5787a9..e71b46f 100644 --- a/src/mesa/main/uniform_query.cpp +++ b/src/mesa/main

[Mesa-dev] [WIP] i965/fs: Initial support for arb_gpu_shader_fp64

execution/vs-out-fs-in-double: fail fp64/preprocessor/vs-input-double.vert: pass fp64/execution/built-in-functions/fs-trunc-double-large: fail fp64/execution/built-in-functions/fs-modf-double: skip fp64/execution/built-in-functions/fs-unpackDouble2x32: pass Topi Pohjolainen (25): i965: Lower DFRACEX

[Mesa-dev] [WIP 04/25] i965: Tell backend register about double precision type

Signed-off-by: Topi Pohjolainen Signed-off-by: Tapani P\344lli Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp

[Mesa-dev] [WIP 08/25] i965/fs: Add support for double precision uniform loading

Unfortunately the safety assertion needs to be dropped as the amount occupied by different types of uniforms is not the same anymore. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.cpp | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src

[Mesa-dev] [WIP 05/25] i965/fs: Prepare virtual registers for double precision floats

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index e2e942c..bec7418 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [WIP 01/25] i965: Lower DFRACEXP/DLDEXP

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 187470c..ddef818 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 10/25] i965/fs: Double precision to single conversion support

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 2 +- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 13 - 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 03/25] i965: Determine size of double precision float register

This is used to determine how many registers an instruction reads and writes as well as for offseting register region into a desired component. Signed-off-by: Topi Pohjolainen Signed-off-by: Tapani P\344lli Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_reg.h | 2 ++ 1 file

[Mesa-dev] [WIP 06/25] i965/fs: Take double float into account in register offsets

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.h | 4 +++- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index

[Mesa-dev] [WIP 12/25] i965: Add helper telling if a register is scalar

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_reg.h | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h index cf2ef13..7cf748f 100644 --- a/src/mesa/drivers/dri/i965/brw_reg.h +++ b/src/mesa

[Mesa-dev] [WIP 17/25] i965/fs: Make generator to emit two instructions for double floats

TODO: 3-src operations Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 39 + 1 file changed, 39 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 92f19e2..a5e3475

[Mesa-dev] [WIP 16/25] i965/gen7: Add support for double precision constant operands

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index c352631..fa3fc41 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 15/25] i965/gen8: Add support for double precision constant operands

Signed-off-by: Topi Pohjolainen Signed-off-by: Tapani P\344lli Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_fs.cpp | 8 src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +++ src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 07/25] i965/fs: Prepare live interval analysis for double precision

TODO: Prevent double precision being split between push and pull. Perhaps it would be easiest just to force them into pull. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.cpp | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers

[Mesa-dev] [WIP 11/25] i965/fs: Prepare register allocator for double precision floats

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.h| 1 + src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 29 +++ 2 files changed, 30 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h

[Mesa-dev] [WIP 19/25] i965/fs: Collect results for double precision conditionals

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.cpp | 43 src/mesa/drivers/dri/i965/brw_fs.h | 3 +++ 2 files changed, 46 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index

[Mesa-dev] [WIP 20/25] i965/gen7: Add support for loading double float scalars in 16-width

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_eu.h | 4 src/mesa/drivers/dri/i965/brw_eu_emit.c | 24 2 files changed, 28 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 22d5a0a

[Mesa-dev] [WIP 13/25] i965/fs: Add pack_double_2x32 virtual opcode

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/brw_fs.h | 5 ++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 96 ++ 3 files changed, 102 insertions(+) diff --git a/src/mesa/drivers/dri

[Mesa-dev] [WIP 09/25] i965/fs: Generator support for converting double to float

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 2 ++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 45 ++ 2 files changed, 47 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 21/25] i965/fs/gen7: Add generator support for loading double precision uniforms

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/brw_fs.h | 3 +++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 32 ++ 3 files changed, 36 insertions(+) diff --git a/src/mesa/drivers/dri

[Mesa-dev] [WIP 24/25] i965/fs: Add unpack_double_2x32 virtual opcode

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 2 + src/mesa/drivers/dri/i965/brw_fs.h | 5 +++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 52 ++ 3 files changed, 59 insertions(+) diff --git a/src/mesa/drivers/dri

[Mesa-dev] [WIP 22/25] i965: Add helper telling if uniform is double and requires special load

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_shader.cpp | 36 src/mesa/drivers/dri/i965/brw_shader.h | 2 ++ 2 files changed, 38 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 25/25] i965/fs: Add support for ir_unop_unpack_double_2x32

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 2 ++ src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b

[Mesa-dev] [WIP 18/25] i965/fs: Generate two instructions for double precision comparison

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_eu_emit.c| 6 ++ src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 7 --- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [WIP 14/25] i965/fs: Add support for ir_unop_pack_double_2x32

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_fs.h | 2 ++ .../drivers/dri/i965/brw_fs_channel_expressions.cpp | 3 +++ src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 20 3 files changed, 25 insertions(+) diff --git a/src

[Mesa-dev] [WIP 23/25] i965/fs: Lower double precision scalars into vectors

On gen7 the hardware supports only single precision scalar operands. This patch modifies fs_visitor to allocate temporary general registers and to manually copy the original 64-bits into the temporary 8- or 16-wide vector depending on the execution size. Signed-off-by: Topi Pohjolainen --- src

[Mesa-dev] [PATCH] i965/meta/hack: Prepare stencil blit for ARB_texture_stencil8

This allows _mesa_base_tex_format() to be fixed to use correct extension when choosing format for stencil, ARB_texture_stencil8 and not ARB_stencil_texturing. No piglit regressions on BDW. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 4 src/mesa

[Mesa-dev] [PATCH 01/18] i965: Refactor rb surface setup to allow caller to store offsets

Notice that in gen7_wm_surface_state.c there is also indentation change in the surrounding code removing tabs. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 8 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 28 --- src

[Mesa-dev] [PATCH 03/18] i965: Refactor and expose brw_upload_binding_table()

Read and write parts of the state stage are also split into explicit arguments allowing future patches to use constant program data. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 21 ++--- src/mesa/drivers/dri/i965/brw_state.h | 7

[Mesa-dev] [PATCH 10/18] i965: Pass integer format flag as parameter to surface setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 +++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +++--- src/mesa/drivers/dri/i965/gen8_surface_state.c| 5 +++-- 4 files

[Mesa-dev] [PATCH 04/18] i965: Remove dependency to tex object in default color setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_sampler_state.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c index c4bd949..c78e2e3

[Mesa-dev] [PATCH 08/18] i965: Move tex miptree and format resolving into dispatcher

All hardware platforms have this in common, so do it in the hardware independent dispatcher. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30 --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 07/18] i965/gen8: Use miptree format in the surface setup

No functional change but this allows to drop the texture object's mesa format in later patches. Stencil buffer has fixed hardware format corresponding to fixed mesa format. (This is in fact already specfically tested in intel_fbo.c::intel_validate_framebuffer()). Signed-off-by: Topi Pohjol

[Mesa-dev] i965: Batch emission refactoring

with formatting. Topi Pohjolainen (18): i965: Refactor rb surface setup to allow caller to store offsets i965: Expose and refactor brw_update_renderbuffer_surfaces() i965: Refactor and expose brw_upload_binding_table() i965: Remove dependency to tex object in default color setup i965: Ref

[Mesa-dev] [PATCH 06/18] i965: Move texture buffer dispatch into single location

All generations do the same exacr dispatch and it could be therefore done in the hardware independent stage. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 3 --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 32 +++ src/mesa

[Mesa-dev] [PATCH 18/18] i965/gen8: Expose state base address setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 3 +++ src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index

[Mesa-dev] [PATCH 05/18] i965: Refactor sampler state setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_sampler_state.c | 60 +-- src/mesa/drivers/dri/i965/brw_state.h | 9 2 files changed, 47 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa

[Mesa-dev] [PATCH 17/18] i965/ps/gen8: Refactor state uploading

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 12 + src/mesa/drivers/dri/i965/gen8_ps_state.c | 74 --- 2 files changed, 59 insertions(+), 27 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 14/18] i965/wm/gen6: Refactor program offset setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 8 + src/mesa/drivers/dri/i965/gen6_wm_state.c | 56 ++- 2 files changed, 41 insertions(+), 23 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 15/18] i965/wm/gen6: Refactor push constant state uploading

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 5 src/mesa/drivers/dri/i965/gen6_wm_state.c | 50 ++- 2 files changed, 34 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 13/18] i965: Pass slice details as parameters for surface setup

Also changed a couple of direct shifts into SET_FIELD(). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 3 ++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 30 +-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14

[Mesa-dev] [PATCH 02/18] i965: Expose and refactor brw_update_renderbuffer_surfaces()

Note that brw_update_renderbuffer_surfaces() already had a helper variable which was used in parallel to direct access of the current draw buffer of the context. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h| 5 +++ src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 12/18] i965: Pass texture target as parameter for surface setup

Also changed a couple of direct shifts into SET_FIELD(). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 11 +-- src

[Mesa-dev] [PATCH 09/18] i965: Move texture swizzle resolving into dispatcher

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 +++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 17 ++--- src/mesa/drivers/dri/i965/gen8_surface_state.c

[Mesa-dev] [PATCH 11/18] i965: Refactor effective depth calculation

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 +-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +-- src/mesa/drivers/dri/i965/gen8_surface_state.c| 8 +--- 4

[Mesa-dev] [PATCH 16/18] i965/ps/gen7: Refactor state uploading

Now the uploading depends only on the input parameters instead of consulting the current gl-state. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 9 + src/mesa/drivers/dri/i965/gen7_wm_state.c | 58 --- 2 files changed, 46

[Mesa-dev] [PATCH 06/16] i965/blorp: Prepare for attributes other than render position

setup always uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional attributes. Hence the change makes the two (blorp and regular) consistent. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 5 +++-- src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++- src

[Mesa-dev] i965: Blorp state setup refactors

This series introduces virtual member functions for blorp parameters that know how certain part of the batch is to be programmed for the shader in question. This will be taken advantage of later on when I add support for launching glsl-based programs. Topi Pohjolainen (16): i965/blorp: Remove

[Mesa-dev] [PATCH 10/16] i965/blorp: Use virtual function for wm/ps configuration

submission (gen6/7_blorp_exec()). This will be exploited even further in the subsequent patches when one more program type is added - the one representing programs compiled from real glsl-sources. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 7 --- src/mesa

[Mesa-dev] [PATCH 05/16] i965/blorp: Remove unused arguments

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 7 ++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 20 +++- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 +++--- 3 files changed, 12 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers

[Mesa-dev] [PATCH 01/16] i965/blorp: Remove constant parameter

This was still needed when we had support for blorp clears but now this is fixed to nop. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 1 - src/mesa/drivers/dri/i965/brw_blorp.h| 8 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 11 --- 3

[Mesa-dev] [PATCH 11/16] i965/blorp: Move push const setup for the parameter type to handle

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +- src/mesa/drivers/dri/i965/brw_blorp.h| 7 ++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +++--- src/mesa/drivers/dri/i965/gen6_blorp.h | 2 +- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 14/16] i965/blorp/gen7: Move surface setup for the parameter type to handle

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++ src/mesa/drivers/dri/i965/gen7_blorp.cpp | 55 ++-- 2 files changed, 34 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 04/16] i965/gen7/blorp: Remove unused arguments

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 75 1 file changed, 28 insertions(+), 47 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index d841346..c9e7cb7 100644

[Mesa-dev] [PATCH 03/16] i965/blorp: Allow caller to provide sampler settings

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 4 +++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +-- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 3 ++- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 09/16] i965/blorp: Prepare drawing rectangle for flipped coordinates

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 4f4d752..21c8423 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 16/16] i965/blorp: Move multisample setup for parameter type to handle

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 2 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 14 ++ src/mesa/drivers/dri/i965/gen7_blorp.cpp | 5 + 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 15/16] i965/blorp: Move vertex uploading for parameter type to handle

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 6 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 11 +-- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 13/16] i965/blorp/gen6: Move surface setup for the parameter type to handle

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 5 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 50 ++-- 2 files changed, 34 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 07/16] i965/blorp: Allow blend state to be set for multiple render targets

Original blorp writes only one buffer per shader invocation. Once the launch mechanism is shared with glsl-based programs there will be need for supporting multiple render targets. Also drop the always constant color write disable settings. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers

[Mesa-dev] [PATCH 12/16] i965/blorp: Move sampler setup for the parameter type to handle

Also move the gen >= 7 specific logic into gen6_blorp.ccp, this will help to avoid more duplication when corresponding logic for glsl-based programs is added. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 9 +++--- src/mesa/drivers/dri/i965/gen6_blorp.cpp |

[Mesa-dev] [PATCH 08/16] i965/blorp: Add support for layered rendering

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 6 -- src/mesa/drivers/dri/i965/brw_blorp.h| 4 +++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 2 +- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +- 4 files changed, 9 insertions(+), 5 deletions(-) diff

[Mesa-dev] [PATCH 02/16] i965/blorp: Refactor vertex buffer state setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 60 ++-- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index e45705a..6c139ec 100644

[Mesa-dev] [PATCH 0.5/18] i965/gen8: Use constant pointers for reading miptree details

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 011c685..b9bbb73 100644 --- a/src/mesa

[Mesa-dev] i965: Don't use gl-context for fbo-blits

skip vertex shader, clip and viewport transformation in strips&fans (SF) but to provide the vertices directly from vertex fetcher (VF) to the windower (WM). Topi Pohjolainen (14): i965/blorp/gen7: Support for loading glsl-based fragment shaders i965/blorp/gen6: Support for loading glsl-b

[Mesa-dev] [PATCH 12/14] i965/blorp/gen7: Expose state setup applicable to gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 36 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 20 +- 2 files changed, 46 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa

[Mesa-dev] [PATCH 07/14] i965/blorp: Add support for setting up surfaces for glsl-based blits

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 3 +++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++ src/mesa/drivers/dri/i965/gen7_blorp.cpp | 7 +++ 3 files changed, 40 insertions(+) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 14/14] i965/blorp/gen8: Execution support

-based programs using the gen-aware jump tables that the core i965 batch submission mechanism provides. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_blorp.cpp| 6 +- src/mesa/drivers/dri/i965/brw_blorp.h | 12 + sr

[Mesa-dev] [PATCH 11/14] i965/blorp/gen7: Prepare re-using for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 7ee62f7..d41d592 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [PATCH 01/14] i965/blorp/gen7: Support for loading glsl-based fragment shaders

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 15 + src/mesa/drivers/dri/i965/brw_blorp.h| 41 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 + src/mesa/drivers/dri/i965/gen7_blorp.cpp | 54

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