CC: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 9 +++
src/mesa/drivers/dri/i965/gen7_wm_state.c | 98 ++++++++++++++++++++-----------
2 files changed, 74 insertions(+), 33 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 26fdae6..5a52a74 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -264,6 +264,15 @@ void brw_update_renderbuffer_surfaces(struct brw_context
*brw,
/* gen7_wm_state.c */
void
+gen7_upload_wm_state(struct brw_context *brw,
+ const struct gl_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo, int min_inv_per_frag,
+ bool kill_enable, bool color_buffer_write_enable,
+ bool msaa_enabled, bool statistic_enable,
+ bool line_stipple_enable, bool polygon_stipple_enable);
+
+void
gen7_upload_ps_state(struct brw_context *brw,
const struct gl_fragment_program *fp,
const struct brw_stage_state *stage_state,
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index b918275..b3fa5be 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -32,63 +32,53 @@
#include "program/prog_statevars.h"
#include "intel_batchbuffer.h"
-static void
-upload_wm_state(struct brw_context *brw)
+void
+gen7_upload_wm_state(struct brw_context *brw,
+ const struct gl_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo, int min_inv_per_frag,
+ bool kill_enable, bool color_buffer_write_enable,
+ bool msaa_enabled, bool statistic_enable,
+ bool line_stipple_enable, bool polygon_stipple_enable)
{
- struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
uint32_t dw1, dw2;
- /* _NEW_BUFFERS */
- bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
-
dw1 = dw2 = 0;
- dw1 |= GEN7_WM_STATISTICS_ENABLE;
+
+ if (statistic_enable)
+ dw1 |= GEN7_WM_STATISTICS_ENABLE;
+
dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
- /* _NEW_LINE */
- if (ctx->Line.StippleFlag)
+ if (line_stipple_enable)
dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
- /* _NEW_POLYGON */
- if (ctx->Polygon.StippleFlag)
+ if (polygon_stipple_enable)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
- if (fp->program.Base.InputsRead & VARYING_BIT_POS)
+ if (fp->InputsRead & VARYING_BIT_POS)
dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
dw1 |= prog_data->barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
- /* _NEW_COLOR, _NEW_MULTISAMPLE */
- /* Enable if the pixel shader kernel generates and outputs oMask.
- */
- if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
- ctx->Multisample.SampleAlphaToCoverage ||
- prog_data->uses_omask) {
+ if (kill_enable)
dw1 |= GEN7_WM_KILL_ENABLE;
- }
- /* _NEW_BUFFERS | _NEW_COLOR */
- if (brw_color_buffer_write_enabled(brw) || writes_depth ||
- dw1 & GEN7_WM_KILL_ENABLE) {
+ if (color_buffer_write_enable || writes_depth ||
+ dw1 & GEN7_WM_KILL_ENABLE)
dw1 |= GEN7_WM_DISPATCH_ENABLE;
- }
+
if (multisampled_fbo) {
- /* _NEW_MULTISAMPLE */
- if (ctx->Multisample.Enabled)
+ if (msaa_enabled)
dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
else
dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
- if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program,
false) > 1)
+ if (min_inv_per_frag > 1)
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
else
dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
@@ -97,9 +87,8 @@ upload_wm_state(struct brw_context *brw)
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
}
- if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
+ if (fp->SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
- }
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
@@ -108,6 +97,49 @@ upload_wm_state(struct brw_context *brw)
ADVANCE_BATCH();
}
+static void
+upload_wm_state(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw->fragment_program);
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+
+ /* _NEW_BUFFERS */
+ const bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
+
+ /* _NEW_LINE */
+ const bool line_stipple_enable = ctx->Line.StippleFlag;
+
+ /* _NEW_POLYGON */
+ const bool polygon_stipple_enable = ctx->Polygon.StippleFlag;
+
+ /* _NEW_COLOR, _NEW_MULTISAMPLE
+ * Enable if the pixel shader kernel generates and outputs oMask.
+ */
+ const bool kill_enable = prog_data->uses_kill || ctx->Color.AlphaEnabled ||
+ ctx->Multisample.SampleAlphaToCoverage ||
+ prog_data->uses_omask;
+
+ /* _NEW_MULTISAMPLE */
+ const bool msaa_enabled = ctx->Multisample.Enabled;
+
+ const int min_inv_per_frag =
+ _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false);
+
+ /* Rendering against the gl-context is always taken into account. */
+ const bool statistic_enable = true;
+
+ /* _NEW_BUFFERS | _NEW_COLOR */
+ gen7_upload_wm_state(brw, &fp->program.Base, prog_data,
+ multisampled_fbo, min_inv_per_frag,
+ kill_enable, brw_color_buffer_write_enabled(brw),
+ msaa_enabled, statistic_enable,
+ line_stipple_enable, polygon_stipple_enable);
+}
+
const struct brw_tracked_state gen7_wm_state = {
.dirty = {
.mesa = _NEW_BUFFERS |
--
1.9.3
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