Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 +
src/mesa/drivers/dri/i965/brw_fs.h | 5 +++
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 52 ++++++++++++++++++++++++++
3 files changed, 59 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 186d09a..d01f1c3 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -921,6 +921,8 @@ enum opcode {
FS_OPCODE_SET_SIMD4X2_OFFSET,
FS_OPCODE_PACK_HALF_2x16_SPLIT,
FS_OPCODE_PACK_DOUBLE_2x32,
+ FS_OPCODE_UNPACK_DOUBLE_2x32_X,
+ FS_OPCODE_UNPACK_DOUBLE_2x32_Y,
FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
FS_OPCODE_PLACEHOLDER_HALT,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index c51aae4..4de501a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -773,6 +773,11 @@ private:
struct brw_reg hi,
struct brw_reg lo);
+ void generate_unpack_double_2x32_half(fs_inst *inst,
+ struct brw_reg dst,
+ struct brw_reg src,
+ bool is_2nd_half);
+
void generate_shader_time_add(fs_inst *inst,
struct brw_reg payload,
struct brw_reg offset,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 39dc563..fabab96 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1507,6 +1507,50 @@ fs_generator::generate_pack_double_2x32(fs_inst *inst,
brw_MOV(p, dst_2nd_half, lo);
}
+/**
+ * Split either high or low (is_2nd_half) 32-bits of given double precision
+ * float element(s) into given vector of 32-bit elements.
+ *
+ * High 32-bits in terms of SIMD8 with vector source:
+ *
+ * +--+--+--+--+--+--+--+--+ +--+--+--+--+--+--+--+--+
+ * dst.reg |H0|H1|H2|H3|H4|H5|H6|H7| src.reg |H0|L0|H1|L1|H2|L2|H3|L3|
+ * +--+--+--+--+--+--+--+--+ +--+--+--+--+--+--+--+--+
+ * src.reg+1 |H4|L4|H5|L5|H6|L6|H7|L7|
+ * +--+--+--+--+--+--+--+--+
+ *
+ * High 32-bits in terms of SIMD8 with scalar source:
+ *
+ * +--+--+--+--+--+--+--+--+ +--+--+--+--+--+--+--+--+
+ * dst.reg |H0|H0|H0|H0|H0|H0|H0|H0| src.reg |H0|L0| | | | | | |
+ * +--+--+--+--+--+--+--+--+ +--+--+--+--+--+--+--+--+
+ */
+void
+fs_generator::generate_unpack_double_2x32_half(fs_inst *inst,
+ struct brw_reg dst,
+ struct brw_reg src,
+ bool is_2nd_half)
+{
+ assert(brw->gen >= 7);
+ assert(dst.type == BRW_REGISTER_TYPE_UD);
+ assert(src.type == BRW_REGISTER_TYPE_DF);
+
+ src.type = BRW_REGISTER_TYPE_UD;
+
+ if (is_2nd_half)
+ src.subnr += 4;
+
+ if (!brw_is_scalar(src)) {
+ assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
+ assert(src.vstride == BRW_VERTICAL_STRIDE_8);
+ src.width = BRW_WIDTH_8;
+ src.hstride = BRW_HORIZONTAL_STRIDE_2;
+ src.vstride = BRW_VERTICAL_STRIDE_16;
+ }
+
+ brw_MOV(p, dst, src);
+}
+
void
fs_generator::generate_uniform_double_float_load(const fs_inst *inst,
struct brw_reg dst,
@@ -2063,6 +2107,14 @@ fs_generator::generate_code(const cfg_t *cfg)
generate_pack_double_2x32(inst, dst, src[0], src[1]);
break;
+ case FS_OPCODE_UNPACK_DOUBLE_2x32_X:
+ generate_unpack_double_2x32_half(inst, dst, src[0], false);
+ break;
+
+ case FS_OPCODE_UNPACK_DOUBLE_2x32_Y:
+ generate_unpack_double_2x32_half(inst, dst, src[0], true);
+ break;
+
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
generate_unpack_half_2x16_split(inst, dst, src[0]);
--
1.8.3.1
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