Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_eu.h | 4 ++++
src/mesa/drivers/dri/i965/brw_eu_emit.c | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 22d5a0a..2d28cfc 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -325,6 +325,10 @@ void brw_shader_time_add(struct brw_compile *p,
struct brw_reg payload,
uint32_t surf_index);
+void brw_copy_double_float_scalar(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg src);
+
/**
* Return the generation-specific jump distance scaling factor.
*
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index c58a4b6..8c8ac36 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2906,3 +2906,27 @@ void brw_shader_time_add(struct brw_compile *p,
0 /* response length */,
false /* header present */);
}
+
+void brw_copy_double_float_scalar(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg src)
+{
+ const struct brw_context *brw = p->brw;
+ brw_inst *insn = brw_alu1(p, BRW_OPCODE_MOV, dst, src);
+
+ assert(brw->gen == 7);
+
+ /* Double precision float scalar isn't supported by IVB. Is has to be
+ * loaded into a vector manually. In SIMD8 mode it is possible to treat the
+ * double precision float as a pair of single precision floats using
+ * register region rx <0;2,1>.
+ * In SIMD16 this won't work as the latter half would use rx+1 as source.
+ * Hence emit two SIMD8 instructions manually both using rx as the source.
+ */
+ if (p->compressed) {
+ brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
+ ++dst.nr;
+ insn = brw_alu1(p, BRW_OPCODE_MOV, dst, src);
+ brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
+ }
+}
--
1.8.3.1
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