On Tue, Jan 19, 2016 at 05:41:40PM +0100, Eduardo Lima Mitev wrote:
> Hello,
>
> This is an RFC series adding support for the ARB_internalformat-query2
> extension:
>
> https://www.opengl.org/registry/specs/ARB/internalformat_query2.txt
>
> The corresponding bug is being tracked at:
>
> https:
On Fri, Jan 29, 2016 at 04:52:54PM +1100, Timothy Arceri wrote:
> In GLES 3.1+ and GL 4.4+ there is no guarantee that interpolation
> qualifiers will match between stages so we cannot safely pack
> varyings using the current packing pass in Mesa.
>
> We also disable packing on outward facing SSO a
On Sat, Feb 06, 2016 at 01:20:30PM +0100, Kai Wasserbäch wrote:
> Hey Vinson,
> I would say the test is wrong. If I sort as a human, "NV_" comes before
> "NVX_".
>
> And running this through sort (the tool), it agrees:
>
> $ echo -e "NVX_gpu_memory_info\nNV_blend_square" | sort -d
> NV_blend_squ
From: Nanley Chery
v2: Use gl_renderbuffer::{Width,Height} (Jason)
Cc: "11.0 11.1"
Signed-off-by: Nanley Chery
---
src/mesa/main/image.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c
ind
From: Nanley Chery
Formatting patch split out for easy reviewing.
Signed-off-by: Nanley Chery
---
src/mesa/main/readpix.c | 58 -
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
From: Nanley Chery
The fast path for Intel's ReadPixels() unintentionally omits clipping
the specified area to a valid one. Rather than clip in various
corner-cases, perform this operation in the API validation stage.
The bug in intel_readpixels_tiled_memcpy() showed itself when the w
From: Nanley Chery
The clipping is performed higher up in the call-chain.
Signed-off-by: Nanley Chery
---
src/mesa/main/readpix.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index a5b74bc..56e9d60
From: Nanley Chery
RGBA8 and BGRA8 unorm formats are compatible with the various
mem_copy functions. Their sRGB counterparts are also compatible
because they're also color-renderable (of importance when the
specified resource is a readbuffer) and they share the same
physical layout.
Signe
On Thu, Feb 11, 2016 at 03:22:35PM -0500, Ilia Mirkin wrote:
Reviewed-by: Nanley Chery
> This fixes
>
> dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.depth_stencil_mode_integer
>
> and a few related tests.
>
> Signed-off-by: Ilia Mirkin
> ---
>
From: Nanley Chery
When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
required to flush to zero the UNORM16 channel values that would be
denormalized. This is specifically required for the values: 1, 2, and 3.
Fixes the 14 failing tests in:
dEQP-GLES3
From: Nanley Chery
Enable drivers to use their own implementation of this method instead of
the mesa default. Since the drivers that currently overwrite
dd_function_table::CompressedTexSubImage also overwrite
::CompressedTexImage, there should be no behavioral change.
Signed-off-by: Nanley
From: Nanley Chery
Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.
With this change, we are no longer failing the 14 tests from:
dEQP-GLES3
From: Nanley Chery
Sampling from an ETC2 texture is supported from Gen8 onwards.
While ASTC_LDR is supported on Gen9, the logic to handle such
formats has not yet been implemented in the driver.
Fixes dEQP-VK.api.info.format_properties.compressed_formats.
Bugzilla: https://bugs.freedesktop.org
From: Nanley Chery
Sampling from an ETC2 texture is supported on Bay Trail and
from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
logic to handle such formats has not yet been implemented in
the driver.
Fixes dEQP-VK.api.info.format_properties.compressed_formats.
v2: Enable ETC2 for
On Fri, Apr 22, 2016 at 05:22:13PM -0700, Jason Ekstrand wrote:
> On Fri, Apr 22, 2016 at 4:38 PM, Nanley Chery wrote:
>
> > From: Nanley Chery
> >
> > Sampling from an ETC2 texture is supported on Bay Trail and
> > from Gen8 onwards. While ASTC_LDR is supported on
On Fri, Apr 22, 2016 at 04:23:59PM -0700, Kenneth Graunke wrote:
> On Tuesday, April 12, 2016 3:30:14 PM PDT Nanley Chery wrote:
> > From: Nanley Chery
> >
> > When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
> > required to flush to zero the
From: Nanley Chery
Fixes some failures in dEQP-VK.api.info.image_format_properties.* and
enables the test group to execute without assert failing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_formats.c | 2 +-
1 file changed
From: Nanley Chery
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
"Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all cases, the base int
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 29 +
2 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index 40104a2
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 1654fc6..203a065 100644
--- a/src/mesa/main
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions.c | 3 +++
src/mesa/main/mtypes.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index c82416a..daf16f9 100644
--- a/src/mesa/main/extensions.c
+++ b
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 8ced579..d1dfb7a 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa
From: Nanley Chery
This patch series adds support for the KHR_texture_compression_astc_{ldr,hdr}
extensions. The last two commits enable support for Skylake systems.
Some rendering issues were encountered during testing, so there is some more
work to be done on this feature. The Piglit tests
From: Nanley Chery
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/brw_defines.h | 36 +
src/mesa/drivers/dri/i965
From: Nanley Chery
Signed-off-by: Nanley Chery
---
.../glapi/gen/KHR_texture_compression_astc.xml | 40 ++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 2 +-
3 files changed, 42 insertions(+), 1
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 0fd1a36
From: Nanley Chery
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 3 +
src/mesa/main/formats.c | 130
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/intel_extensions.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 18b69a0..91ff6e4 100644
--- a/src/mesa
ere and there. :-)
> --Jason
>
> > Cheers,
> >
> > -ilia
> >
> > P.S. Congrats on your first public patch submission to mesa-dev :)
> >
>
Thanks for the welcome!
- Nanley
> > On Tue, May 19, 2015 at 8:48 PM, Nanley Chery
> wrote:
&
Hi Ilia,
Thanks for finding these errors. I'll have fixes in v2.
- Nanley
On Tue, May 19, 2015 at 7:07 PM, Ilia Mirkin wrote:
> On Tue, May 19, 2015 at 8:48 PM, Nanley Chery
> wrote:
> > From: Nanley Chery
> >
> > Signed-off-by: Nanley Cher
On Tue, May 19, 2015 at 7:22 PM, Ilia Mirkin wrote:
>
> On Tue, May 19, 2015 at 10:16 PM, Matt Turner wrote:
> > On Tue, May 19, 2015 at 5:48 PM, Nanley Chery wrote:
> >> From: Nanley Chery
> >>
> >> Signed-off-by: Nanley Chery
> >> ---
> &
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 6a77c91..10e2a87 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa
From: Nanley Chery
v2: alphabetize the extensions.
remove OES ASTC extension.
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions.c | 2 ++
src/mesa/main/mtypes.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 0fd1a36
From: Nanley Chery
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa
From: Nanley Chery
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 3 +
src/mesa/main/formats.c | 130
From: Nanley Chery
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Along with changing the cpp definition, the units for
From: Nanley Chery
v2: remove extra newline.
Signed-off-by: Nanley Chery
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
2 files changed, 6 insertions(+), 24 deletions(-)
diff --git a/src/mesa/main/format_info.py b/src/mesa/main
From: Nanley Chery
ALIGN and ROUND_DOWN_TO both require that the alignment value passed into the
macro be a power of two in the comments. Using software assertions verifies
this to be the case.
Signed-off-by: Nanley Chery
---
src/mesa/main/macros.h | 10 --
1 file changed, 8
From: Nanley Chery
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
v2: remove extra newlines.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/brw_defines.h | 34 +
src/mesa
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 1654fc6..203a065 100644
--- a/src/mesa/main
From: Nanley Chery
v2: correct the spelling of the sRGB variants.
remove spaces around "=" when setting the enum value.
Signed-off-by: Nanley Chery
---
.../glapi/gen/KHR_texture_compression_astc.xml | 40 ++
src/mapi/glapi/gen/Makefile.am
From: Nanley Chery
v2: remove OES ASTC extension reference.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index
From: Nanley Chery
- Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
- Don't pass more parameters than necessary.
- Minor code simplifications.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/brw_tex_layout.c
From: Nanley Chery
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Signed-off-by: Nanley Chery
---
src/mesa/swrast/s_texfetch.c | 239
From: Nanley Chery
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
"Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all cases, the base int
From: Nanley Chery
In this revision, comments have been taken into account and most rendering
issues have been fixed. Unfortunately, when rendering the reference sRGB
textures, the HW-loaded compressed versions are still rendered darker than
the pre-decoded SW ones. The Piglit tests for this
From: Nanley Chery
Since _mesa_image_row_stride() is used to calculate the destination's
row stride, we can read pixels into a destination sub-rectangle (whose
width is smaller than the destination buffer).
Signed-off-by: Nanley Chery
---
The fast-path is confirmed to work with the foll
From: Nanley Chery
This field is no longer needed.
Signed-off-by: Nanley Chery
---
src/intel/isl/isl.h | 9 -
src/intel/isl/isl_surface_state.c | 8
src/intel/vulkan/anv_image.c | 33 +++--
3 files changed, 7 insertions(+), 43
From: Nanley Chery
Match the comment stated above the assignment.
Signed-off-by: Nanley Chery
---
src/intel/isl/isl_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index fe8f07c
From: Nanley Chery
In addition to making the height addition more understandable, this
future-proofs the code for new tiling modes and keeps the image
height as small as possible.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta_blit.c | 13 +++--
1 file changed, 11
From: Nanley Chery
The limit for these textures is 2048 not 1024.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 8aa1e61..5367375 100644
From: Nanley Chery
This can be reverted if the only other consumer, anv_meta_blit2d(),
uses a different method.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta.h | 11 +++
src/intel/vulkan/anv_meta_blit.c | 2 +-
2 files changed, 12 insertions(+), 1 deletion(-)
diff
From: Nanley Chery
In addition to demystifying the value being added to the height,
this future-proofs the code for new tiling modes and keeps the
image height as small as possible.
v2: Actually use the smallest height possible.
Signed-off-by: Nanley Chery
---
src/intel/vulkan
From: Nanley Chery
The new organization is as follows:
* anv_meta_blit.c: Blit and state setup/teardown commands
* anv_meta_copy.c: Copy and update commands
* anv_meta_blit2d.c: 2D Blitter API commands
Also, change the formatting to contain most lines
within 80 columns.
Signed-off-by: Nanley
From: Nanley Chery
Follow the convention for non-static functions.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta.h| 2 +-
src/intel/vulkan/anv_meta_blit.c | 4 ++--
src/intel/vulkan/anv_meta_blit2d.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta_blit2d.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_meta_blit2d.c
b/src/intel/vulkan/anv_meta_blit2d.c
index d49b470..6f07342 100644
--- a/src/intel/vulkan
From: Nanley Chery
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta_blit.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_meta_blit.c b/src/intel/vulkan/anv_meta_blit.c
index ecd4d2d..82b79b8 100644
--- a/src/intel/vulkan
On Tue, Mar 08, 2016 at 10:41:24AM -0800, Anuj Phogat wrote:
> On Fri, Mar 4, 2016 at 2:03 PM, Nanley Chery wrote:
> > From: Nanley Chery
> >
> > In addition to making the height addition more understandable, this
> > future-proofs the code for new tiling modes and ke
driver upgrade has broken my, previously working code, causing
> > massive flickering and graphical artifacts.
> >
> > git bisect have shown, that this is the breaking change:
> >
> > commit 7ebbc3946ae9cffb3c3db522dcbe2f1041633164 (refs/bisect/bad)
> >
On Wed, Mar 16, 2016 at 07:25:56PM -0700, Kenneth Graunke wrote:
> Stencil texturing is required by ES 3.1. Apparently we never actually
> turned it on, and we missed some necessary code.
>
> Fixes nine dEQP-GLES31.functional tests:
>
> stencil_texturing.format.stencil_index8_2d
> texture.border
From: Nanley Chery
Prepare Image extents and offsets for internal consumption by assigning
the default values implicitly defined by the spec. Fixes textures on
several Vulkan demos in which the VkImageCopy depth is set to zero when
copying a 2D image.
Signed-off-by: Nanley Chery
---
src/intel
From: Nanley Chery
Prepare Image extents and offsets for internal consumption by assigning
the default values implicitly defned by the spec. Fixes textures on
several Vulkan demos in which the VkImageCopy depth is set to zero when
copying a 2D image.
v2 (Jason Ekstrand):
Replace "prep&
From: Nanley Chery
This function differs from the open-coded implementation in that the
ImageView's width is determined by the caller and is not unconditionally
set to match the number of texels within the surface's pitch.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_met
From: Nanley Chery
This is required to create multiple, horizontally adjacent, max-width
images from one blit2d surface. This is also required for more accurate
width specification of surfaces within a larger surface (which is seen
as the smaller surface's enclosing region).
Note
On Thu, Jun 02, 2016 at 04:27:26PM -0700, Jason Ekstrand wrote:
> This was causing problems if the user tried to copy to/from the stencil
> portion of a combined depth/stencil image.
>
> Signed-off-by: Jason Ekstrand
> Cc: Nanley Chery
> ---
> src/intel/vulkan
From: Nanley Chery
Signed-off-by: Nanley Chery
---
docs/devinfo.html | 7 +++
1 file changed, 7 insertions(+)
diff --git a/docs/devinfo.html b/docs/devinfo.html
index f5d23ab..489d263 100644
--- a/docs/devinfo.html
+++ b/docs/devinfo.html
@@ -684,6 +684,8 @@ To add a new GL extension to
From: Nanley Chery
Signed-off-by: Nanley Chery
---
docs/devinfo.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/devinfo.html b/docs/devinfo.html
index 8ebf80f..70141ae 100644
--- a/docs/devinfo.html
+++ b/docs/devinfo.html
@@ -703,6 +703,7 @@ To add a new GL extension to Mesa you
From: Nanley Chery
Signed-off-by: Nanley Chery
---
docs/devinfo.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/devinfo.html b/docs/devinfo.html
index 70141ae..f5d23ab 100644
--- a/docs/devinfo.html
+++ b/docs/devinfo.html
@@ -686,7 +686,7 @@ To add a new GL
On Thu, Jun 02, 2016 at 05:05:09PM -0700, Nanley Chery wrote:
> On Thu, Jun 02, 2016 at 04:27:26PM -0700, Jason Ekstrand wrote:
> > This was causing problems if the user tried to copy to/from the stencil
> > portion of a combined depth/stencil image.
> >
> > Signed-off
On Mon, Jun 06, 2016 at 02:47:54PM -0700, Ian Romanick wrote:
> This matches what we've been doing since you reworked the extension
> string handling. This series is
>
> Reviewed-by: Ian Romanick
Thanks!
- Nanley
>
> On 06/03/2016 11:04 AM, Nanley Chery wrote:
On Wed, May 25, 2016 at 12:52:38PM -0700, Matt Turner wrote:
> On Wed, May 25, 2016 at 12:17 PM, Samuel Pitoiset
> wrote:
> > This fixes use of compute shaders with some NVIDIA GL 4.3 samples which
> > require a compat profile.
>
> I'm confused.
>
> The samples you're talking about... use 4.3 co
On Tue, Jun 07, 2016 at 04:28:48PM -0700, Nanley Chery wrote:
> On Wed, May 25, 2016 at 12:52:38PM -0700, Matt Turner wrote:
> > On Wed, May 25, 2016 at 12:17 PM, Samuel Pitoiset
> > wrote:
> > > This fixes use of compute shaders with some NVIDIA GL 4.3 samples whic
On Tue, Jun 07, 2016 at 04:45:39PM -0700, Ian Romanick wrote:
> On 06/07/2016 04:28 PM, Nanley Chery wrote:
> > On Wed, May 25, 2016 at 12:52:38PM -0700, Matt Turner wrote:
> >> On Wed, May 25, 2016 at 12:17 PM, Samuel Pitoiset
> >> wrote:
> >>> This fixes
gt; Author: Samuel Pitoiset
> > > > Date: Wed May 25 21:17:24 2016 +0200
> > > >
> > > > mesa: Let compute shaders work in compatibility profiles
> > > >
> > > > The extension is already advertised in compatibility profile, but
> > &
From: Nanley Chery
Add guards to prevent dereferencing NULL dynamic pipeline state.
This fixes a segfault seen in the McNopper demo, VKTS_Example09.
Signed-off-by: Nanley Chery
Cc: "12.0"
---
src/intel/vulkan/anv_pipeline.c | 51 ++---
1 file c
From: Nanley Chery
This is useful for the next commit which will use this information.
Signed-off-by: Nanley Chery
Cc: "12.0"
---
src/intel/vulkan/anv_pipeline.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/in
From: Nanley Chery
To reduce confusion, clarify that the state being copied is not dynamic.
This agrees with the Vulkan spec's usage of the term. Various sections
specify that the various pipeline state which have VkDynamicState enums
(e.g. viewport, scissor, etc.) may or may not be dy
On Fri, Jun 10, 2016 at 04:33:06PM -0700, Jason Ekstrand wrote:
> On Fri, Jun 10, 2016 at 4:12 PM, Nanley Chery wrote:
>
> > From: Nanley Chery
> >
> > Add guards to prevent dereferencing NULL dynamic pipeline state.
> >
> > This fixes a segfault seen
From: Nanley Chery
To reduce confusion, clarify that the state being copied is not dynamic.
This agrees with the Vulkan spec's usage of the term. Various sections
specify that the various pipeline state which have VkDynamicState enums
(e.g. viewport, scissor, etc.) may or may not be dy
From: Nanley Chery
Add guards to prevent dereferencing NULL dynamic pipeline state. Asserts
of pCreateInfo members are moved to the earliest points at which they
should not be NULL.
This fixes a segfault seen in the McNopper demo, VKTS_Example09.
v2: Fix disabled rasterization check (Jason
On Fri, Jun 10, 2016 at 06:19:12PM -0700, Jason Ekstrand wrote:
> On Fri, Jun 10, 2016 at 6:03 PM, Nanley Chery wrote:
>
> > From: Nanley Chery
> >
> > Add guards to prevent dereferencing NULL dynamic pipeline state. Asserts
> > of pCreateInfo members are moved t
From: Nanley Chery
Add guards to prevent dereferencing NULL dynamic pipeline state. Asserts
of pCreateInfo members are moved to the earliest points at which they
should not be NULL.
This fixes a segfault seen in the McNopper demo, VKTS_Example09.
v3 (Jason Ekstrand):
- Fix disabled
From: Nanley Chery
To reduce confusion, clarify that the state being copied is not dynamic.
This agrees with the Vulkan spec's usage of the term. Various sections
specify that the various pipeline state which have VkDynamicState enums
(e.g. viewport, scissor, etc.) may or may not be dy
On Sun, Jun 12, 2016 at 4:23 PM, Ilia Mirkin wrote:
> Previously we were only restricting based on ES/non-ES-ness and whether
> the overall enable bit had been flipped on. However we have been adding
> more fine-grained restrictions, such as based on compat profiles, as
> well as specific ES vers
On Mon, Jun 13, 2016 at 9:16 AM, Ilia Mirkin wrote:
> On Mon, Jun 13, 2016 at 12:11 PM, Emil Velikov
> wrote:
> > Hi Ilia,
> >
> > On 13 June 2016 at 00:23, Ilia Mirkin wrote:
> >
> >> @@ -81,6 +81,7 @@ MAIN_FILES = \
> >> main/execmem.c \
> >> main/extensions.c \
> >> m
On Mon, Jun 13, 2016 at 9:08 AM, Ilia Mirkin wrote:
> On Mon, Jun 13, 2016 at 12:03 PM, Nanley Chery
> wrote:
> >
> >
> > On Sun, Jun 12, 2016 at 4:23 PM, Ilia Mirkin
> wrote:
> >>
> >> Previously we were only restricting based on ES/non-ES-nes
This causes tests that attempt to create linear depth buffers on
Gen7+ (unsupported), to be skipped.
Signed-off-by: Nanley Chery
---
src/tests/func/miptree/miptree.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/src/tests/func
Signed-off-by: Nanley Chery
---
src/intel/isl/isl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index ef86228..64aced8 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -989,7 +989,7
This reverts commit 091f1da902c71ac8d3d27b325a118e2f683f1ae5.
Although a user may specify a specfic tiling bit, ISL should still
prevent incompatible tiling/surface combinations.
Signed-off-by: Nanley Chery
---
Prior to patch https://patchwork.freedesktop.org/patch/95338/ ,
this change made
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_image.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 77d9931..b3f5f5c 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan
In the next patch, ISL will unconditionally perform verification of a
surface's tiling and usage. Since it will require that w-tiled images
be stencil buffers, create a stencil surface to copy from a
w-tiled/stencil surface.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta_bli
From: Nanley Chery
Help developers understand the table's organization.
Suggested-by: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions_table.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa
On Wed, Nov 18, 2015 at 12:33 PM, Emil Velikov
wrote:
> Hi Nanley,
>
> On 18 November 2015 at 20:29, Nanley Chery wrote:
> > From: Nanley Chery
> >
> > Help developers understand the table's organization.
> >
> > Suggested-by: Jason Ekstrand
>
From: Nanley Chery
Suggested-by: Marek Olšák
Suggested-by: Emil Velikov
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions_table.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index d12fd9f
From: Nanley Chery
Enable developers to know if the table's alphabetical sorting
is maintained or lost.
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions.h | 1 +
src/mesa/main/tests/Makefile.am | 1 +
src/mesa/main/tests/mesa_extensions.cpp
From: Nanley Chery
Make it easier to determine where to add new extensions.
Performed with the vim sort command.
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions_table.h | 173 +--
1 file changed, 92 insertions(+), 81 deletions(-)
diff --git a/src
o modify the declaration of
_mesa_extension_table to specify a size of MESA_EXTENSION_COUNT.
On Wed, Nov 18, 2015 at 6:01 PM, Nanley Chery wrote:
> > From: Nanley Chery
> >
> > Enable developers to know if the table's alphabetical sorting
> > is maintained or lost.
&g
On Wed, Nov 18, 2015 at 4:08 PM, Emil Velikov
wrote:
> On 18 November 2015 at 23:40, Nanley Chery wrote:
> > On Wed, Nov 18, 2015 at 3:07 PM, Ilia Mirkin
> wrote:
> >>
> >> Why have the count as an entry in the enum? Can't you just do
> >> ARRAY_SI
On Wed, Nov 18, 2015 at 4:17 PM, Emil Velikov
wrote:
> On 18 November 2015 at 22:39, Nanley Chery wrote:
> > On Wed, Nov 18, 2015 at 12:33 PM, Emil Velikov >
> > wrote:
> >>
> >> Hi Nanley,
> >>
> >> On 18 November 2015 at 2
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