From: Nanley Chery <nanley.g.ch...@intel.com>
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index dacaad7..5aadd00 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -124,9 +124,12 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
* Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE "Surface Vertical Alignment" field.
*/
- if (_mesa_is_format_compressed(format))
+ if (_mesa_is_format_compressed(format)) {
+ unsigned int i, j;
+ _mesa_get_format_block_size(format, &i, &j);
/* See comment above for the horizontal alignment */
- return brw->gen >= 9 ? 16 : 4;
+ return brw->gen >= 9 ? j * 4 : 4;
+ }
if (format == MESA_FORMAT_S_UINT8)
return brw->gen >= 7 ? 8 : 4;
--
2.4.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
