This is now dead code.
---
src/mesa/drivers/dri/i965/brw_fs.h | 21 -
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 608 ---
2 files changed, 629 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index fed5d23..d
---
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 36 ++--
2 files changed, 15 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 64f89d4..fed5d2
= GRF &&
> + (!inst->predicate || inst->opcode == BRW_OPCODE_SEL)) {
> for (unsigned i = 0; i < inst->regs_written; i++) {
> for (int c = 0; c < 4; c++) {
>if (inst->dst.writemask & (1 << c)) {
Look
This seems rather silly and would lead to memory corruption if the
size of a VGRF was allowed to be zero.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs
Francisco Jerez writes:
> This seems rather silly and would lead to memory corruption if the
> size of a VGRF was allowed to be zero.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +++---
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/src/
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size will be used for bounds checking with some image
formats and will be us
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
---
src/mesa/drivers/dri/i965/brw_context.h | 10 +++-
src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 25
src/mesa/drivers/dri/i965/brw_state.h| 4 ++
src/mesa/drivers/dri/i965/brw_
v2: Add CS support.
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_gs.c | 1 +
src/mesa/drivers/dri/i965/brw_vs.c | 3 ++-
src/mesa/drivers/dri/i965/brw_wm.c | 3 ++-
4 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw
This cleans up fs_inst::regs_read() slightly by disentangling the
calculation of "components" from the handling of message payload
arguments. This will also simplify the SIMD lowering and logical send
message lowering passes, because it will avoid expressions like
'regs_read * REG_SIZE / component
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 1062ded..a996676 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -405
Another resend of the i965 compiler-related changes for
ARB_shader_image_load_store, reworked to make use of the SIMD lowering
infrastructure introduced in a previous series [1]. For a
self-contained branch in testable form see [2].
[1] http://lists.freedesktop.org/archives/mesa-dev/2015-July/089
Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit easily.
v2: Drop VEC4 suport.
v3: Reimplement in terms of logical send opcodes.
---
src/mesa/drivers/dri/i965/Makefile.sources | 2 +
.
Define some utility functions to query the bitfield layout of a given
image format and whether it satisfies a number of more or less
hardware-specific properties.
v2: Drop VEC4 suport.
v3: Add SKL support.
---
src/mesa/drivers/dri/i965/brw_fs_surface_builder.h | 148 +
1 file
This will be handy to avoid some ugly ternary operators in the next
patch, like:
fs_reg reg = (size == 0 ? null_reg_ud() : vgrf(..., size));
Because a zero-size register allocation is guaranteed not to ever be
read or written we can just return the null register. Another
possibility would be to
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 63 +++-
1 file changed, 55 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a996676..0b0c5e1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+
Define a function to calculate the memory address of the image
location given by a vector of coordinates. This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and
Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determi
Images take up zero uniform slots in the nir_shader::num_uniforms
calculation, but nir_setup_uniforms needs to be executed even if the
program has no non-image uniforms so the driver-specific image
parameters are uploaded. nir_setup_uniforms is a no-op if there are
really no uniforms, so checking
v2: Move the image_params array back to brw_stage_prog_data.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 31 +++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/driv
These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results. Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB
Reviewed-by: Paul Berry
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 6b3bd12..5a5e308 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.
v2: Drop VEC4 suport.
v3: Rebase.
---
.../drivers/dri/i965/brw_fs_surface_builder.cpp| 216 +
src/mesa/drivers/dri/i965/brw_fs_surface_builder.h | 17 ++
2 files changed, 233 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
b/src/mesa/drive
Rewrite the NIR atomic counter intrinsics translation code making use
of the recently introduced surface builder. This will allow the
removal of some of the functionality duplicated between the visitor
and surface builder.
v2: Drop VEC4 suport.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 49 +
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
separately as individual sources, like:
typed_surface_write_logical null, coordinates, source, surface,
num_coordinates, num
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0b0c5e1..0d97474 100644
--- a/src/mesa/drivers/dri/i965/
v2: Move the image_params array back to brw_stage_prog_data.
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 50 +++-
2 files changed, 43 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/sr
---
src/mesa/drivers/dri/i965/brw_fs.h | 7 --
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 112 ---
3 files changed, 5 insertions(+), 127 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b
Image variables need to allocate additional uniform slots over
nir_shader::num_uniforms. nir_setup_uniforms() overwrites the values
imported from the SIMD8 visitor and then exits early before entering
the nir_shader::uniforms loop, so image uniforms are never re-created.
Instead leave the imported
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 76297b7..9a1fb4b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 149 +++
1 file changed, 149 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 31024b7..76297b7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++
Jason Ekstrand writes:
> A few comments below. Mostly just asking for explanation.
>
> 1-3 are
>
> Reviewed-by: Jason Ekstrand
>
> Obviously, don't merge 4/4 until it actually has users.
> --Jason
Thanks.
>
> On Thu, Jul 16, 2015 at 8:35 AM, Francisco Jer
Jason Ekstrand writes:
> On Sat, Jul 18, 2015 at 7:34 AM, Francisco Jerez
> wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 66
>> +---
>> 1 file changed, 49 insertions(+), 17 deletions(-)
>>
>> diff --git a/sr
Jason Ekstrand writes:
> On Sat, Jul 18, 2015 at 7:34 AM, Francisco Jerez
> wrote:
>> So that it's left uninitialized by LOAD_PAYLOAD, we only need to
>> reserve space for it in the message since it will be initialized
>> implicitly by the generator.
>>
Jason Ekstrand writes:
> On Thu, Jul 16, 2015 at 8:41 AM, Francisco Jerez
> wrote:
>> The only non-trivial thing it still has to do is figure out where to
>> take the src/dst depth values from and predicate the instruction if
>> discard is in use. The manual SIMD unr
Jason Ekstrand writes:
> On Sat, Jul 18, 2015 at 7:34 AM, Francisco Jerez
> wrote:
>> This should match the set of cases in which we currently call fail()
>> or no16() from the emit_texture_*() methods and the ones in which
>> emit_texture_gen4() enables the SIMD16 wo
Kenneth Graunke writes:
> On Thursday, July 16, 2015 06:41:16 PM Francisco Jerez wrote:
>> The logical variant is largely equivalent to the original opcode but
>> instead of taking a single payload source it expects the arguments
>> that make up the payload separately as ind
This seems to have been multiplying by stride twice since
fs_inst::regs_read/regs_written were changed to return the value in
register units rather than in dispatch_width-wide components. The
value returned by fs_inst::regs_read() already takes into account the
stride so it's wrong to do it again
Jason Ekstrand writes:
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.cpp | 63
>> +++-
>> 1 file changed, 55 insertions(+), 8 deletions(-)
>>
>> diff --git a/
Jason Ekstrand writes:
> On Wed, Jul 22, 2015 at 12:31 AM, Francisco Jerez
> wrote:
>> Jason Ekstrand writes:
>>
>>> A few comments below. Mostly just asking for explanation.
>>>
>>> 1-3 are
>>>
>>> Reviewed-by: Jason Ekstrand
Jason Ekstrand writes:
> On Wed, Jul 22, 2015 at 10:02 AM, Francisco Jerez
> wrote:
>> Jason Ekstrand writes:
>>
>>> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
>>> wrote:
>>>> ---
>>>> src/mesa/drivers/dri/i965/brw_fs.cpp
Jason Ekstrand writes:
> On Wed, Jul 22, 2015 at 12:43 AM, Francisco Jerez
> wrote:
>> Jason Ekstrand writes:
>>
>>> On Sat, Jul 18, 2015 at 7:34 AM, Francisco Jerez
>>> wrote:
>>>> So that it's left uninitialized by LOAD_PAYLOAD, we
Jason Ekstrand writes:
> On Wed, Jul 22, 2015 at 10:05 AM, Francisco Jerez
> wrote:
>> Jason Ekstrand writes:
>>
>>> On Wed, Jul 22, 2015 at 12:31 AM, Francisco Jerez
>>> wrote:
>>>> Jason Ekstrand writes:
>>>>
>>>>&g
Francisco Jerez writes:
> Jason Ekstrand writes:
>
>> On Wed, Jul 22, 2015 at 10:05 AM, Francisco Jerez
>> wrote:
>>> Jason Ekstrand writes:
>>>
>>>> On Wed, Jul 22, 2015 at 12:31 AM, Francisco Jerez
>>>> wrote:
>>>>&
Jason Ekstrand writes:
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> Define bitfield packing, unpacking and type conversion operations in
>> terms of which the image format conversion code will be implemented.
>> These don't directly know about i
urface format to
use for a given GLSL format is shared between the compiler and the
state-setup code, see brw_lower_mesa_image_format() in "i965: Implement
surface state set-up for shader images.".
Thanks.
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> v2:
Jason Ekstrand writes:
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> v2: Move the image_params array back to brw_stage_prog_data.
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.h | 1 +
>> src/mesa/driver
Jason Ekstrand writes:
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> Reviewed-by: Paul Berry
>
> I'm sure that Paul still thinks this patch does what the commit
> message says. However, does the r-b really still apply to the rest of
> it?
>
T
Jason Ekstrand writes:
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 149
>> +++
>> 1 file changed, 149 insertions(+)
>>
>> diff --git a/src/mesa/driv
x27;m having a lot of trouble getting any
> further splitting the x/y into major/minor.
>
> Cc'ing chad. He knows miptree layouts far better than I do. Maybe
> this is all obvious to someone familiar with the calculations.
>
> --Jason
>
> On Tue, Jul 21, 2015 at 9:38 AM,
Jason Ekstrand writes:
> *whew*, I've made it through the entire series...
>
Thanks!
> On Tue, Jul 21, 2015 at 9:38 AM, Francisco Jerez
> wrote:
>> Another resend of the i965 compiler-related changes for
>> ARB_shader_image_load_store, reworked to
Jason Ekstrand writes:
> On Thu, Jul 23, 2015 at 3:55 AM, Francisco Jerez
> wrote:
>> Francisco Jerez writes:
>>
>>> Jason Ekstrand writes:
>>>
>>>> On Wed, Jul 22, 2015 at 10:05 AM, Francisco Jerez
>>>> wrote:
>>>>
Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determi
v2: Drop VEC4 suport.
v3: Rebase.
v4: Move array coordinate workaround into the surface builder.
---
.../drivers/dri/i965/brw_fs_surface_builder.cpp| 244 +
src/mesa/drivers/dri/i965/brw_fs_surface_builder.h | 20 ++
2 files changed, 264 insertions(+)
diff --git a/src/mes
v2: Move array coordinate workaround into the surface builder.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 106 +++
1 file changed, 106 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 805f782..318
Accounting for the padding required for 1D arrays in certain cases.
---
.../drivers/dri/i965/brw_fs_surface_builder.cpp| 52 ++
1 file changed, 52 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
b/src/mesa/drivers/dri/i965/brw_fs_surface_bu
hu, Jul 23, 2015 at 10:33 AM, Francisco Jerez
> wrote:
>> Accounting for the padding required for 1D arrays in certain cases.
>> ---
>> .../drivers/dri/i965/brw_fs_surface_builder.cpp| 52
>> ++
>> 1 file changed, 52 insertions(+)
>>
&
Chris Wilson writes:
> On Sat, Oct 03, 2015 at 05:57:05PM +0300, Francisco Jerez wrote:
>> Jordan Justen writes:
>>
>> > From: Francisco Jerez
>> >
>> > Fixes
>> > arb_shader_image_load_store/execution/load-from-cleared-image.shader_test
Antía Puentes writes:
> Hi Matt,
>
> thanks for your suggestions.
>
> On dom, 2015-10-11 at 10:35 -0700, Matt Turner wrote:
>> I don't believe it's valuable to port the opt_peephole_sel() pass to
>> the vec4 backend. With NIR (since NIR essentially performs the same
>> optimization), the opt_peep
Iago Toral Quiroga writes:
> This fixes the following test:
>
> [require]
> GL >= 3.3
> GLSL >= 3.30
> GL_ARB_shader_storage_buffer_object
>
> [fragment shader]
> #version 330
> #extension GL_ARB_shader_storage_buffer_object: require
>
> buffer SSBO {
> mat4 sm4;
> };
>
>
> mat4 um4;
>
> void
Antía Puentes writes:
> On lun, 2015-10-12 at 15:55 +0300, Francisco Jerez wrote:
>> Antía Puentes writes:
>> > On dom, 2015-10-11 at 10:35 -0700, Matt Turner wrote:
>> >> I would expect big improvements in the vec4 backend from making its
>> >> copy pr
Iago Toral writes:
> On Tue, 2015-10-13 at 15:17 +0300, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> > This fixes the following test:
>> >
>> > [require]
>> > GL >= 3.3
>> > GLSL >= 3.30
>> > GL_ARB
Alejandro Piñeiro writes:
> On 13/10/15 23:36, Matt Turner wrote:
>> On Tue, Oct 13, 2015 at 1:49 AM, Alejandro Piñeiro
>> wrote:
>>> On 13/10/15 03:10, Matt Turner wrote:
Looks like this is causing an intermittent failure on HSW in our
Jenkins system (but I'm not able to reproduce lo
Hi Marta,
Marta Lofstedt writes:
> From: Marta Lofstedt
>
> The split of Uniform blocks and shader storage block only loops
> up to MESA_SHADER_FRAGMENT and igonres compute shaders.
> This cause segfault when running the OpenGL ES 3.1 CTS tests
> with GL_ARB_compute_shader enabled.
>
> Signed-o
"Lofstedt, Marta" writes:
> I have found a couple of more places in linker.cpp where we loop up to
> MESA_SHADER_FRAGMENT.
> Should these now also be up to MESA_SHADER_COMPUTE instead?
>
Some might be oversights like this, but I guess in some cases a loop up
to MESA_SHADER_FRAGMENT might be the
> V2: Changed to use MESA_SHADER_STAGES instead of
> MESA_SHADER_COMPUTE
>
> Signed-off-by: Marta Lofstedt
Reviewed-by: Francisco Jerez
> ---
> src/glsl/linker.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/glsl/linker.cpp b/src
Jordan Justen writes:
> On 2015-10-13 22:49:08, Iago Toral wrote:
>> On Tue, 2015-10-13 at 09:44 -0700, Jordan Justen wrote:
>> > On 2015-10-13 05:17:37, Francisco Jerez wrote:
>> > > Iago Toral Quiroga writes:
>> > >
>> > > >
Alejandro Piñeiro writes:
> ---
>
> This patch implements the idea proposed by Francisco Jerez. With this
> change, even adding the new condition pointed by Matt Turner on the
> "2/5 i965/vec4: adding vec4_cmod_propagation optimization", the shader-db
> numbers re
do, I'm okay with either:
- Just drop this hunk in order to stick to the letter of the BSpec and
always pass a header together with typed surface read messages. I
have the strong suspicion though that the docs are just being
inaccurate and the header is in fact unnecessary on HSW+.
Neil Roberts writes:
> Just a thought, would it be better to move this check into the
> eliminate_find_live_channel optimisation? That way it could catch
> sources that become immediates through later optimisations. One problem
> with this that I've seen before is that eliminating the
> FIND_LIVE
Hi Abdiel,
Abdiel Janulgue writes:
> Signed-off-by: Abdiel Janulgue
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index a8594a
Kristian Høgsberg writes:
> On Mon, Oct 19, 2015 at 4:19 AM, Francisco Jerez
> wrote:
>> Neil Roberts writes:
>>
>>> Just a thought, would it be better to move this check into the
>>> eliminate_find_live_channel optimisation? That way it could catch
>&g
Iago Toral Quiroga writes:
> This allows us to re-use the results of previous ssbo loads in situations
> that are safe (i.e. when there are no stores, atomic operations or
> memory barriers in between).
>
> This is particularly useful for things like matrix multiplications, where
> for a mat4 buf
Iago Toral writes:
> On Tue, 2015-10-20 at 13:22 +0300, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> > This allows us to re-use the results of previous ssbo loads in situations
>> > that are safe (i.e. when there are no stores, atomic operations o
Kristian Høgsberg writes:
> On Tue, Oct 20, 2015 at 3:16 AM, Francisco Jerez
> wrote:
>> Kristian Høgsberg writes:
>>
>>> On Mon, Oct 19, 2015 at 4:19 AM, Francisco Jerez
>>> wrote:
>>>> Neil Roberts writes:
>>>>
>>
Iago Toral writes:
> Hi Curro,
>
> On Tue, 2015-10-20 at 14:18 +0300, Francisco Jerez wrote:
>> Iago Toral writes:
>>
>> > On Tue, 2015-10-20 at 13:22 +0300, Francisco Jerez wrote:
>> >> Iago Toral Quiroga writes:
>> >>
>> >>
Timothy Arceri writes:
> On Fri, 2015-10-16 at 10:28 +1100, Timothy Arceri wrote:
>> Cc: Francisco Jerez
>
> Hi Curro,
>
> Just pinging you on this patch and patch 5. These are the final two
> patches remaining unreviewed before I can enable arrays of arrays.
>
&
Ben Widawsky writes:
> Cc: Francisco Jerez
> Signed-off-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i9
Timothy Arceri writes:
> On Wed, 2015-10-21 at 13:06 +0300, Francisco Jerez wrote:
>> Timothy Arceri writes:
>>
>> > On Fri, 2015-10-16 at 10:28 +1100, Timothy Arceri wrote:
>> > > Cc: Francisco Jerez
>> >
>> > Hi Curro,
>> >
sulting code is inferior, I am not super attached to the patch.
>
> Cc: Francisco Jerez
> Signed-off-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 18 ++
> src/mesa/drivers/dri/i965/brw_fs.cpp| 21 +++--
> 2 files cha
Iago Toral writes:
> On Wed, 2015-10-21 at 13:00 +0300, Francisco Jerez wrote:
>> Iago Toral writes:
>>
>> > Hi Curro,
>> >
>> > On Tue, 2015-10-20 at 14:18 +0300, Francisco Jerez wrote:
>> >> Iago Toral writes:
>> >>
a missed hardcoded logical position in get_lowered_simd_width (Ben)
> Add an assertion to make sure the component numbering is correct (Ben)
>
> Cc: Matt Turner
> Cc: Francisco Jerez
> Signed-off-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 22 +++
Connor Abbott writes:
> On Thu, Oct 22, 2015 at 7:21 AM, Iago Toral Quiroga wrote:
>> I implemented this first as a separate optimization pass in GLSL IR [1], but
>> Curro pointed out that this being pretty much a restricted form of a CSE pass
>> it would probably make more sense to do it inside
Connor Abbott writes:
> On Thu, Oct 22, 2015 at 10:37 AM, Francisco Jerez
> wrote:
>> Connor Abbott writes:
>>
>>> On Thu, Oct 22, 2015 at 7:21 AM, Iago Toral Quiroga
>>> wrote:
>>>> I implemented this first as a separate optimization pass
r when
the remaining compiler infrastructure is fixed to handle them properly.
With that change this patch is:
Reviewed-by: Francisco Jerez
> Kristian
signature.asc
Description: PGP signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
fset_reg = get_nir_src(instr->src[1]);
>} else {
> - const_offset_bytes = instr->const_index[0];
> - bld.MOV(offset_reg, fs_reg(const_offset_bytes));
> + offset_reg = fs_reg(instr->const_index[0]);
>}
>
Reviewed-by: Francisco Jerez
>
>src[i] = val;
> + progress = true;
> + }
> + break;
> +
Reviewed-by: Francisco Jerez
>case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
>case SHADER_OPCODE_BROADCAST:
> inst->src[i] = val;
> --
> 2.6.2
>
> __
*/, length,
> + BRW_PREDICATE_NONE);
> +
> + /* Clear the bits in the writemask that we just wrote, then try
> + * again to see if more channels are left.
> + */
> + writemask &= (15 << (first_component
Kristian Høgsberg Kristensen writes:
> Here's an updated and expanded ssbo optimization series. I found a bit
> of low-hanging fruit around dynamic ssbo array indexing. I removed the
> IMM shortcut in emit_uniformize() and added the constant propagation
> for the read and write opcodes. The resul
Kristian Høgsberg writes:
> On Tue, Oct 20, 2015 at 11:56 AM, Francisco Jerez
> wrote:
>> Kristian Høgsberg writes:
>>
>>> On Tue, Oct 20, 2015 at 3:16 AM, Francisco Jerez
>>> wrote:
>>>> Kristian Høgsberg writes:
>>>>
>>
Abdiel Janulgue writes:
> The 3DSTATE_GATHER_POOL_ALLOC is used to enable or disable the gather
> push constants feature within a context. This patch provides the toggle
> functionality of using gather push constants to program constant data
> within a batch.
>
> Using gather push constants requi
Abdiel Janulgue writes:
> Reserve space in the gather pool where the gathered uniforms are flushed.
>
> Signed-off-by: Abdiel Janulgue
> ---
> src/mesa/drivers/dri/i965/gen6_vs_state.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
>
Francisco Jerez writes:
> Abdiel Janulgue writes:
>
>> Reserve space in the gather pool where the gathered uniforms are flushed.
>>
>> Signed-off-by: Abdiel Janulgue
>> ---
>> src/mesa/drivers/dri/i965/gen6_vs_state.c | 8
>> 1 file chang
Abdiel Janulgue writes:
> If there are UBO constant entries, append them to
> stage_state->push_const_size.
> The gather pool contains the combined entries of both ordinary uniforms
> and UBO constants.
>
> Signed-off-by: Abdiel Janulgue
> ---
> src/mesa/drivers/dri/i965/gen6_vs_state.c | 20 +
Francisco Jerez writes:
> Abdiel Janulgue writes:
>
>> If there are UBO constant entries, append them to
>> stage_state->push_const_size.
>> The gather pool contains the combined entries of both ordinary uniforms
>> and UBO constants.
>>
>> Signed
Abdiel Janulgue writes:
> The resource streamer is able to gather and pack sparsely-located
> constant data from any buffer object by a referring to a gather table
> This patch adds support for keeping track of these constant data
> fetches into a gather table.
>
> The gather table is generated f
Abdiel Janulgue writes:
> To be able to refer to a constant buffer, the resource streamer needs
> to index it with a hardware binding table entry. This blankets the ubo
> buffers with hardware binding table indices.
>
> Gather constants hardware fetches in 16-entry binding table blocks.
> So we n
Abdiel Janulgue writes:
> Assign the uploaded uniform block with hardware binding table indices.
> This is indexed by the resource streamer to fetch the constant buffers
> referred to by our gather table entries.
>
> Signed-off-by: Abdiel Janulgue
> ---
> src/mesa/drivers/dri/i965/gen6_vs_state
Abdiel Janulgue writes:
> Now that we consider UBO constants as push constants, we need to include
> the sizes of the UBO's constant slots in the visitor's uniform slot sizes.
> This information is needed to properly pack vector constants tightly next to
> each other.
>
> Signed-off-by: Abdiel Ja
Abdiel Janulgue writes:
> This patch generates the gather table entries for ordinary uniforms
> if they are present. The uniform constants here will later be packed
> together with UBO constants.
>
> Signed-off-by: Abdiel Janulgue
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 18 ++
Matt Turner writes:
> On Fri, Oct 23, 2015 at 11:23 AM, Francisco Jerez
> wrote:
>> Abdiel Janulgue writes:
>>
>>> This patch generates the gather table entries for ordinary uniforms
>>> if they are present. The uniform constants here will later be pa
101 - 200 of 3036 matches
Mail list logo
