On Wed, Jun 10, 2015 at 03:34:50PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
1 and 2 are:
Reviewed-by: Ben Widawsky
[snip]
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On Wed, Jun 10, 2015 at 05:01:44PM -0700, Nanley Chery wrote:
> From: Nanley Chery
>
> On Gen9+, vertical and horizontal alignment values for compressed textures are
> equal to the pre-Gen9 value squared. Each miplevel must be aligned to this
> value.
>
> Signed-off-by: Nanley Chery
While not
On Tue, Jun 16, 2015 at 03:46:26PM -0700, Kenneth Graunke wrote:
> On Tuesday, June 16, 2015 10:08:38 PM Meng, David wrote:
> > Hi:
> > I am new to this email list. I would like to get a help from you.
> >
> > I found a patch with number of 47790 which supports Intel Broadwell(BDW)
> > system ge
On Tue, Jun 16, 2015 at 01:53:40PM +0100, Neil Roberts wrote:
> brw_miptree_layout_2d tries to ensure that mt->total_width is a
> multiple of the compressed block size, presumably because it wouldn't
> be possible to make an image that has a fraction of a block. However
> it was doing this by align
sionality == GLSL_SAMPLER_DIM_CUBE) {
> + ir->lod_info.lod = expr(ir_binop_add,
> + expr(ir_unop_log2, rho),
> + new(mem_ctx) ir_constant(-1.0f));
> + } else {
> + ir->lod_info.lod = expr(ir_unop_log2, rho);
> + }
>
> progress = true;
> return visit_continue;
Patch seems to do what it's advertising. I am not really an expert here, but
fwiw:
Reviewed-by: Ben Widawsky
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because of the ongoing changes with MOCS setup. It
is what is being used/tested, so it's included in the series.
The chosen values are the old values left shifted. That was also an arbitrary
choice.
Cc: Francisco Jerez
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_define
These match the ones defined in the kernel. The only one tested by us is 0x0a84.
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 8d757aa..4d8b419 100644
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_device_info.c | 16
src/mesa/drivers/dri/i965/brw_device_info.h | 1 +
4 files changed, 19 insertions(+)
diff -
NOTE: I can no longer find where this workaround is documented. In my notes it
is required for BXT A*, and B*. I'm happy to drop the patch, but I figured I'd
put it here for completeness.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 3 +++
1 file
On Thu, Jun 18, 2015 at 04:19:36PM -0700, Matt Turner wrote:
> Fixes a performance problem caused by commit b639ed2f.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90895
Ken spotted this in review.
/me hides
Reviewed-by: Ben Widawsky
> ---
> src/mesa/d
---
scripts/tags/mesa_tags.sh | 4
1 file changed, 4 deletions(-)
diff --git a/scripts/tags/mesa_tags.sh b/scripts/tags/mesa_tags.sh
index 4404b92..c8e2098 100755
--- a/scripts/tags/mesa_tags.sh
+++ b/scripts/tags/mesa_tags.sh
@@ -3,13 +3,9 @@
rm cscope.*
rm tags
git ls-files src/mesa/dri
hu Jun 18 16:14:50 2015 -0700
i965: Add missing braces around if-statement.
This logic should match that of the v1 of my halign patch series.
Cc: Kenneth Graunke
Cc: Matt Turner
Reported-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Sorry, ignore this. I had script fail. Real patch coming up.
On Thu, Jun 18, 2015 at 06:44:35PM -0700, Ben Widawsky wrote:
> ---
> scripts/tags/mesa_tags.sh | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/scripts/tags/mesa_tags.sh b/scripts/tags/mesa_tags.sh
> inde
rease code
size with no possible performance benefit.
Same patch for FS coming up.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri
Just like the previous patch but for the FS.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index
because we don't want to spill inside loops, and by doing
> the same thing for if's you're actually discouraging spills inside an
> if block.
>
> On Fri, Jun 19, 2015 at 5:21 PM, Ben Widawsky
> wrote:
> > If we have a register that needs spilling in an if/els
On Fri, Jun 19, 2015 at 08:04:51PM -0700, Matt Turner wrote:
> On Fri, Jun 19, 2015 at 6:53 PM, Connor Abbott wrote:
> > I don't think this is doing what you think it's doing. This code is
> > for calculating the *cost* of spills, so a higher cost means a lower
> > priority for choosing the regist
r all
> generations at one place.
>
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 97
> --
> 1 file changed, 79 insertions(+), 18 deletions(-)
>
> diff --git a/src/mesa/driv
I am shocked this is the only place we do this...
On Wed, Jun 10, 2015 at 03:30:48PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletio
1-4 (with/without changes) are:
Reviewed-by: Ben Widawsky
On Wed, Jun 10, 2015 at 03:30:49PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 30
> +++---
> 1 file chan
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 86
> +--
> 1 file changed, 80 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa
On Thu, Jun 18, 2015 at 03:41:50PM -0700, Kenneth Graunke wrote:
> On Wednesday, June 17, 2015 03:50:13 PM Ben Widawsky wrote:
> > On gen9+ MOCS is an index into a table. It is 7 bits, and AFAICT, bit 0 is
> > for
> > doing encrypted reads.
> >
> > I don't r
ns_overlap() function.
> > Simplify horizontal and vertical alignment computations.
> >
> > Signed-off-by: Anuj Phogat
> > Cc: Ben Widawsky
> > ---
> > src/mesa/drivers/dri/i965/intel_blit.c | 295
> > ++-
> > src/mesa
;
> V2: Delete min/max buffer size restrictions not valid for i965+.
> Remove redundant align to tile size statements.
> Remove some redundant code now when there are no min/max buffer size.
>
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> -
Hi. Feel free to Cc me on patches of this nature. I am far behind on mesa-dev,
and no longer read intel-gfx. I'm probably one of the sensible people to look at
this...
On Tue, Jun 23, 2015 at 01:21:27PM +0100, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must a
On Wed, Jun 24, 2015 at 02:29:09PM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > I think this is beginning to infringe upon the definition of align_w.
> > The total width is a function of it's miptree properties and not the
> > compressed block properties,
On Wed, Jun 24, 2015 at 08:12:36PM +, Lecluse, Philippe wrote:
> I Have successfully tested and validate patch 1,3,4 on BXT
> Regards,
> Philippe
> Intel Corporation NV/SA
> Kings Square, Veldkant 31
> 2550 Kontich
> RPM (Bruxelles) 0415.497.718.
> Citibank, Brussels, account 570/1031255/09
>
gen8 had some special restrictions which don't seem to carry over to gen9.
Quoting the spec for SKL:
"The Z_Height and Z_Width values must equal those present in
3DSTATE_DEPTH_BUFFER incremented by one."
This fixes nothing in piglit (and regresses nothing).
Cc: Jordan Justen
Sig
requirement, but it shouldn't hurt and
probably makes looking a debug slightly easier. Also, if we do ever support
preemption, it should work. One comment inline, and then it's
Reviewed-by: Ben Widawsky
>
> In the HSW PRM, the it doesn't mention that it must always
alloc_strcat(&shProg->InfoLog, sh->InfoLog);
> + else
> +ralloc_strdup(ctx, shProg->InfoLog);
I don't understand what the strdup part is meant to do. Without the else, this
is:
Reviewed-by: Ben Widawsky
Feel free to explain why you need to dup the log
LSL IR for native %s shader %d:\n",
> + stage, shader_prog->Name);
> + _mesa_print_ir(stderr, shader->ir, NULL);
> + fprintf(stderr, "\n\n");
> + }
> } else {
>fprintf(stderr, "ARB_%s_program %d ir for nativ
On Fri, Jun 26, 2015 at 01:23:41PM -0700, Anuj Phogat wrote:
> On Mon, Jun 22, 2015 at 5:23 PM, Anuj Phogat wrote:
> > On Mon, Jun 22, 2015 at 2:53 PM, Ben Widawsky wrote:
> >> On Wed, Jun 10, 2015 at 03:30:47PM -0700, Anuj Phogat wrote:
> >>> Buffers with Yf/Ys t
mesa 10.7 time.
I did think of it, but never broached the subject if we want to send both my
MOCS patch, and the PTE version of this patch to stable.
Anyway, the concept here is definitely
Acked-by: Ben Widawsky
> ---
> Note that this change is based on Ville's "[PATCH 1/2] i965:
ate_at_centroid_modes(const struct gl_fragment_program
> *fprog)
> +{
> + unsigned interp_modes = 0;
> + struct nir_shader *shader = fprog->Base.nir;
> +
> + if (shader == NULL)
> + return 0;
> +
> + nir_foreach_overload(shader, overload) {
> + if (overlo
On Wed, Jul 01, 2015 at 12:33:54AM +0300, Francisco Jerez wrote:
> Ben Widawsky writes:
>
> > On Tue, Jun 30, 2015 at 11:25:42PM +0300, Francisco Jerez wrote:
> >> Instead of relying on hardware defaults the i915 kernel driver is
> >> going program custom MOCS table
Certain compressed formats require this setting. The docs don't go into much
detail as to why it's needed exactly.
This fixes 0 piglit failures with a GBM gpu piglit run.
Signed-off-by: Ben Widawsky
---
I had this one sitting around for almost 2 months. I'm not sure why I did
We don't yet have a use for this state, but initializing it to known values is
always considered wise. In general NULL state can probably go in the misc state
upload, I only put it here because I assume it might be useful at some point.
Signed-off-by: Ben Widawsky
---
I've had
On Wed, Jul 01, 2015 at 04:03:53PM -0700, Ben Widawsky wrote:
> Certain compressed formats require this setting. The docs don't go into much
> detail as to why it's needed exactly.
>
> This fixes 0 piglit failures with a GBM gpu piglit run.
I just ran this again in piglit s
>dw1 |= GEN8_PSX_SHADER_HAS_UAV;
>
It's unclear to me what the downside to always setting this bit would be (I
assume that's the behavior of previous gens).
I also assume this means you're abandoning the other patch, or doing it on top
of this, else you don't want to do it for the centroid case.
Reviewed-by: Ben Widawsky
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ing useful. As soon as I get a
platform to test it on, I will - meanwhile, maybe whomever tested the original
patch the first time around come run this through?
Cc: Matt Turner
Cc: Chad Versace
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/main/streaming-load-memcpy.c | 61
01,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
> GLenum gl_target =
>rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
> - /* FINISHME: Use PTE MOCS o
On Thu, Jul 02, 2015 at 12:58:33PM -0700, Matt Turner wrote:
> On Thu, Jul 2, 2015 at 12:57 PM, Matt Turner wrote:
> > On Wed, Jul 1, 2015 at 4:03 PM, Ben Widawsky
> > wrote:
> >> Certain compressed formats require this setting. The docs don't go into
> >>
t seems to go better with the existing code.
Cc: Matt Turner
Cc: Nanley Chery
Cc: Jordan Justen (aux-hiz needs this too)
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/gen8_surface_state.c | 29 ++
till a bunch of spurious failures, I miss Mark):
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/169/
Signed-off-by: Ben Widawsky
Reviewed-by: Anuj Phogat (v1)
---
I had a minor bug in v1 which prevented me from pushing this sooner. I'd like to
merge this patch unless anyone has complaints?
---
On Thu, Jul 09, 2015 at 09:44:52AM -0700, Ben Widawsky wrote:
> While implementing the workaround in the previous patch I noticed things were
> starting to get a bit messy. Since gen8 works differently enough from gen7, I
> thought splitting it out with be good.
>
> While here,
.jf.intel.com/job/bwidawsk/170/
Signed-off-by: Ben Widawsky
Reviewed-by: Anuj Phogat (v1)
---
src/mesa/drivers/dri/i965/brw_state.h | 6 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 3
On Thu, Jul 02, 2015 at 11:32:03PM -0700, Jordan Justen wrote:
> On 2015-06-25 11:34:59, Ben Widawsky wrote:
> > On Thu, Jun 11, 2015 at 09:04:45PM -0700, Jordan Justen wrote:
> > > + desc[dw++] = 0;
> > > + const uint32_t media_threads =
> > > + br
On Tue, Jun 16, 2015 at 02:21:39PM -0700, Jordan Justen wrote:
> brw_upload_cs_push_constants was based on gen6_upload_push_constants.
This review is based off of 2838833bfd5eb0a87fdacfa1cd6391b50f9c0b8b in your
repository. This patch doesn't apply cleanly in its current form.
>
> Signed-off-by:
On Fri, Jul 10, 2015 at 12:03:54PM -0700, Matt Turner wrote:
> On Thu, Jul 9, 2015 at 11:00 AM, Ben Widawsky
> wrote:
> > While implementing the workaround in the previous patch I noticed things
> > were
> > starting to get a bit messy. Since gen8 works differently
Several mappings require special handling (stencil, etc textures, and depth).
Since I am attempting to clean up the logic which chooses the way in which we
map things, relegating this inflexible part to another part of the function
reduces complexity.
Signed-off-by: Ben Widawsky
---
src/mesa
in a function that is
determining whether or not we should use the blitter, but I tried the
alternatives, and they look worse IMO.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c| 13 +
src/mesa/drivers/dri/i965/intel_blit.h| 3 +++
src/mesa/dr
t
Cc: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 21 ++--
src/mesa/drivers/dri/i965/intel_fbo.c | 6 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +-
src/mesa/drivers/dri/i965/intel_mipmap_t
If I am reading the code correctly, writable mappings and mappings for
compressed miptrees will always end up using calling map_gtt.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
s about 3 times now and I figured I should
finally send it out, since most people I asked think it's a good idea (and none
of them has said it's a bad idea).
Ccing all the people that I've discussed this with...
Cc: Jason Ekstrand
Cc: Chad Versace
Cc: Kenneth Graunke
Cc: Anuj
e this patch can get some comments meanwhile.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 76 +--
1 file changed, 37 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965
On Wed, Jul 01, 2015 at 02:46:32PM +0300, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
I swear I am not trying to nitpick but I don't actually understand what your
goal of the patch is. Could you maybe elaborate a bit on what "reduce the scope
of input in.."
> ---
> src/mesa/driver
On Tue, Jul 14, 2015 at 09:56:08AM -0700, Ben Widawsky wrote:
> A few patches which cleanup the miptree mapping logic. I haven't heavily
> tested
> them yet, which is why I added the RFC label (admittedly I totally ignored the
> unmap path, I hope it just works, but I'll fi
On Wed, Jul 15, 2015 at 11:02:03AM -0700, Connor Abbott wrote:
> On Wed, Jul 15, 2015 at 7:49 AM, Iago Toral wrote:
> > Hi,
> >
> > when we sent the patches for the new nir->vec4 backend we mentioned that
> > we had a few dEQP tests that would fail to link because of register
> > spilling. Now tha
On Thu, Jul 16, 2015 at 01:45:56PM -0700, Chad Versace wrote:
> On Tue 14 Jul 2015, Ben Widawsky wrote:
> > This patch rewrites the logic for determining which method we using for
> > mapping
> > a miptree. It is my intention that that this patch, the required patches
>
On Thu, Jul 16, 2015 at 03:06:48PM -0700, Matt Turner wrote:
> On Tue, Jul 14, 2015 at 9:56 AM, Ben Widawsky
> wrote:
> > This patch rewrites the logic for determining which method we using for
> > mapping
> > a miptree. It is my intention that that this patch, the requ
On Mon, Jul 20, 2015 at 03:35:26PM +0200, Iago Toral wrote:
> Hi,
> On Thu, 2015-07-16 at 08:15 -0700, Jason Ekstrand wrote:
> >
> > On Jul 15, 2015 11:20 PM, "Iago Toral" wrote:
> > >
> > > On Wed, 2015-07-15 at 11:02 -0700, Connor Abbott wrote:
> > > > On Wed, Jul 15, 2015 at 7:49 AM, Iago Tora
0
Observed: 0.50
Probe at (0,0)
Expected: 0.00
Observed: 0.50
Not-Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++--
src/mesa/drivers/dri/i965/gen8_surface_state.c | 8
2 files changed, 6 insertions(+), 10 deletions(-)
the other instances as well. I can make an argument both ways (open
coding it, vs. not). I can rework the next patch if requires.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 12
1 file changed, 12 deletions(-)
diff --git a/src/mesa/drivers/dri
clearing multiple color buffer attachments and can be
observed in the following piglit tests:
spec/arb_framebuffer_object/fbo-drawbuffers-none glclear
spec/ext_framebuffer_multisample/blit-multiple-render-targets 0
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 97
to expect
this to provide large gains in tests which are memory bandwidth limited and
doing many clears.
Ben Widawsky (10):
i965/gen8+: Remove redundant zeroing of surface state
i965/gen8+: Extract color clear surface state
i965/skl: Enable fast color clears on SKL
i965/skl: skip fast
This reverts commit dcd59a9e322edeea74187bcad65a8e56c0bfaaa2.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8
1 file changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f108b75..c723f79 100644
--
This reverts commit 8a0c85b25853decb4a110b6d36d79c4f095d437b.
It's not a strict revert because I don't want to bring back the gen < 9 check at
this point in time.
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/
if (brw->gen >= 9)
+ *height = 2;
+ else
+ *height = 4;
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 54 +
src/mesa/drivers/dri/i965/gen8_surface_state.c | 34
src/mesa/dr
On future generation platforms the color clear value is stored elsewhere in the
surface state. By extracting this logic, we can cleanly implement the difference
in an upcoming patch.
Should have no functional impact.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965
It doesn't actually serve a purpose AFAICT (in fact, I'm not certain what it's
meant to do).
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/m
There is nothing wrong with the code today, but as one modifies the code it
turns out to be not too difficult to mess up the code, and this easy assertion
should catch such driver implementation failures quickly.
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965
er of multisamples. MCS (Multisample
Control Surface) is a special type of CCS."
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_surface_formats.c | 27 +
src/mesa/drivers/dri/i965/gen8_surface_sta
r,
I'm sort of baffled now why I'd see no piglit regressions since the clear color
will *never* be all F.
Either way, I'll drop this patch - but my confusion level has increased.
> Ben Widawsky writes:
>
> > It doesn't actually serve a purpose AFAICT (in fact
On Wed, Oct 14, 2015 at 02:43:24PM +0300, Pohjolainen, Topi wrote:
> On Wed, Oct 14, 2015 at 11:39:03AM +0200, Neil Roberts wrote:
> > Ben Widawsky writes:
> >
> > > The impetus for this patch comes from a seemingly benign statement within
> > > the
> > &
On Wed, Oct 14, 2015 at 08:04:48PM +0300, Pohjolainen, Topi wrote:
> On Wed, Oct 14, 2015 at 09:54:43AM -0700, Ben Widawsky wrote:
> > On Wed, Oct 14, 2015 at 02:43:24PM +0300, Pohjolainen, Topi wrote:
> > > On Wed, Oct 14, 2015 at 11:39:03AM +0200, Neil Roberts wrote:
> >
do change, for now we could certainly assume that SKL is
the base set and future GENs add things.
> Ben Widawsky writes:
>
> > Initially I had this planned as a patch to be squashed in to the enabling
> > patch
> > because there is no point enabling fast clears without
On Tue, Oct 13, 2015 at 08:50:17PM -0700, Ben Widawsky wrote:
> This patch series adds support for fast color clears on SKL as it exists on
> previous generations of hardware minus the new hardware restriction on surface
> formats. Additionally, it adds support for utilizing clear value
still working on implementing meta blits for stencil using this
extension. I think the patches for that are mostly done, but they need more
testing. I'll be posting those separately.
Ben Widawsky (6):
i965: Correct the comment about fb write payload
i965/fs: Enumerate logical fb writes
the patch.
Cc: Francisco Jerez
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 18 ++
src/mesa/drivers/dri/i965/brw_fs.cpp| 21 +++--
2 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
aunke
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri
Cc: Francisco Jerez
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 393f17a..7a5ee1b 100644
--- a/src/mesa
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_defines.h| 5 +++--
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 ++
src/mesa/drivers/dri/i965/brw_fs.h | 2 ++
src/mesa/drivers/dri/i965
Signed-off-by: Ben Widawsky
---
docs/relnotes/11.1.0.html| 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html
index d3dbe9d..9abc6df 100644
--- a/docs/relnotes/11.1.0
This patch is split out for review. It will be squashed before pushing.
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +++-
src/mesa/drivers/dri/i965/brw_fs.h | 2 ++
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 44 +
On Tue, Oct 20, 2015 at 11:56:15AM +0200, Neil Roberts wrote:
> In bfdae9149e0 I disabled the opt_sampler_eot optimisation for TG4
> message types because I found by experimentation that it doesn't work.
> I wrote in the comment that I couldn't find any documentation for this
> problem. However I'v
On Tue, Oct 20, 2015 at 02:52:29PM -0700, Matt Turner wrote:
> On Tue, Oct 20, 2015 at 2:29 PM, Ben Widawsky
> wrote:
> > Gen9 adds the ability to write out a stencil value, so we need to expand the
> > virtual payload by one. Abstracting this now makes that change easier to
&
On Tue, Oct 20, 2015 at 02:57:24PM -0700, Matt Turner wrote:
> On Tue, Oct 20, 2015 at 2:54 PM, Ben Widawsky wrote:
> > On Tue, Oct 20, 2015 at 02:52:29PM -0700, Matt Turner wrote:
> >> On Tue, Oct 20, 2015 at 2:29 PM, Ben Widawsky
> >> wrote:
> >> > Gen9
On Tue, Oct 20, 2015 at 03:17:38PM -0700, Matt Turner wrote:
> On Tue, Oct 20, 2015 at 2:29 PM, Ben Widawsky
> wrote:
> > This patch is split out for review. It will be squashed before pushing.
> > ---
> > src/mesa/drivers/dri/i965/brw_defines.h| 1 +
> &
On Tue, Oct 20, 2015 at 03:19:48PM -0700, Matt Turner wrote:
> On Tue, Oct 20, 2015 at 3:11 PM, Ben Widawsky wrote:
> > On Tue, Oct 20, 2015 at 02:57:24PM -0700, Matt Turner wrote:
> >> On Tue, Oct 20, 2015 at 2:54 PM, Ben Widawsky wrote:
> >> > On Tue, Oct 20,
On Tue, Oct 20, 2015 at 02:48:41PM -0700, Matt Turner wrote:
> On Tue, Oct 20, 2015 at 2:41 PM, Ben Widawsky wrote:
> > On Tue, Oct 20, 2015 at 11:56:15AM +0200, Neil Roberts wrote:
> >> In bfdae9149e0 I disabled the opt_sampler_eot optimisation for TG4
> >> messa
on to make sure the component numbering is correct (Ben)
Cc: Matt Turner
Cc: Francisco Jerez
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 22 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 24 +---
src/mesa/drivers/dri
On Thu, Oct 22, 2015 at 06:44:53PM -0700, Vivek Kasireddy wrote:
> On newer hardware platforms that support rotation, if the gbm
> interface requests to create a rotated scanout buffer via the
> flag __DRI_IMAGE_USE_SCANOUT_ROTATED_90_270, set Y-tiling
> while creating the buffer.
>
> Cc: Kristian
Like other gen8+ hardware, the hardware automatically scales up thread counts
and URB sizes, so there is no need to do anything but add the PCI IDs.
FINISHME: This patch still needs testing before merge.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky
---
include/pci_ids
A few new PCI ids are added here, and one is removed (0x190B) because it no
longer seems to exist anywhere.
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 40 ++--
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/include
On Fri, Oct 23, 2015 at 10:37:29AM -0700, Ben Widawsky wrote:
> Like other gen8+ hardware, the hardware automatically scales up thread counts
> and URB sizes, so there is no need to do anything but add the PCI IDs.
>
> FINISHME: This patch still needs testing before merge.
>
On Fri, Oct 23, 2015 at 01:44:38PM -0400, Ilia Mirkin wrote:
> On Fri, Oct 23, 2015 at 1:37 PM, Ben Widawsky
> wrote:
> > A few new PCI ids are added here, and one is removed (0x190B) because it no
> > longer seems to exist anywhere.
> >
> > Signed-off-by: Ben
This removes ones which aren't used 0x190b, 192a), and adds some new ones. I
kept the original names where possible.
Cc: Kristian Høgsberg
Cc: Damien Lespiau
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 46 ++
1 file change
Cc: Kristian Høgsberg
Cc: Damien Lespiau
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 253ea71..6c8dc73 100644
--- a/intel/intel_chipset.h
+++ b/intel
...@lists.freedesktop.org
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 4
src/mesa/drivers/dri/i965/brw_device_info.c | 4
2 files changed, 8 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 8a42599..626064a
A few new PCI ids are added here, and two are removed (0x190B, 0x192A) because
it no longer seems to exist anywhere.
v2: Update commit message to reflect the removal of 0x192a as well.
Only use ascii characters (Ilia)
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 41
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